Routing the connections on a printed circuit board is a complex and time-consuming activity. On large or dense boards, the process of routing can take a designer considerable time, something that an autorouter can assist with.
Altium Designer's Situs™ autorouter uses a topological-analysis technique to map the board space, which, unlike geometric or shape-based mapping, is not dependent on obstacle shape or coordinates. Topological mapping provides greater flexibility in route path determination and unrestricted routing direction.
The name Situs comes from Situs Analysis, a branch of mathematics that studies the properties of geometric figures or solids that are not normally affected by changes in size or shape, commonly known today as topology.
Autorouting the Board
The Situs Topological Router brings a new approach to the autorouting challenge. It uses advanced topological mapping first to define the routing path, then calls on a variety of proven routing algorithms to convert this 'human-like' path to a high-quality route. As an integral part of the PCB Editor, it follows the PCB electrical and routing rule definitions.
Board Setup
While Situs is straightforward to set up and run, there are certain points you should be aware of to produce optimal routing.
Component Placement
Ultimately, the component placement has the most significant impact on routing performance. Altium Designer's PCB Editor includes a number of tools, such as dynamically optimized connection lines, that allow you to fine tune component placement. The optimal component placement is when the connection lines are as short and least 'tangled' as possible.
Other good design practices include placing components so their pads are on a regular grid (to maximize the amount of free space between the pads for routing), placing similar sized surface mount components exactly opposite each other on double sided boards, and consulting device manufacturers datasheets for decoupling placement guidelines. This is not a complete list of placement considerations, simply a few suggestions.
Keepouts
The router requires a closed boundary, made up of placed keepout objects. Typically, this boundary follows the edge of the board. Placed objects will obey the applicable clearance rule to ensure that they remain a suitable distance away from this boundary, to satisfy any mechanical or electrical clearance requirements that the design may have. The router will also obey keepouts within this outer boundary, as well as layer-specific keepouts.
You can create a closed boundary that follows the edge of the board shape, using the Line/Arc Primitives from Board Shape dialog. For more information about keepouts, see Object Specific Keepouts.
Polygon Pours
Polygon (or copper) pours can be either solid (filled with one or more copper regions) or hatched (constructed from tracks and arcs). A medium to large hatched polygon pour includes a large number of tracks and arcs. While the router can route a board that includes such polygon pours, the sheer number of objects they introduce increases the complexity of the routing process.
Typically you should only place polygon pours prior to routing if they are required, for example, they are being used to construct unusually shaped pre-routing, perhaps the incoming mains routing or a critical ground region. Otherwise it is preferable that polygon pours be added to the design once routing is complete.
Is it Routable?
An autorouter is a human attempt to understand and model the routing process, then replicate that process automatically. If the board contains an area that can not be routed by hand, then it will not be autorouted either. If the router is continually failing on a component or a section of the board then you should attempt to route it interactively. It may be that there are placement or rule configuration issues that make it impossible to route at all.
Pre-routing
Pre-route critical nets and, if it is essential that they are not changed by the routing process, lock them by enabling the Lock All Pre-routes option in the Situs Routing Strategies dialog. Avoid unnecessary locking though; a large number of locked objects can make the routing problem much more difficult.
Differential pairs nets must be manually routed and locked before using the autorouter. If you do not so this, the routing is very likely to change and alter the signal integrity of the differential pair.
Configuring the Design Rules
The term default rule is used to describe a rule with a query scope of All.
If a rule includes Minimum, Preferred and Maximum values, the autorouter will use the Preferred value.
Make sure the routing design rules are appropriate to the board technology you are using. Poorly targeted or inappropriate design rules can lead to very poor autorouting performance. Note that the router obeys all Electrical and Routing design rules, except the Routing Corners rule.
Rules are defined in the PCB Rules and Constraints Editor dialog (Design » Rules), which can be accessed directly from the Situs Routing Strategies dialog.
If a rule includes Minimum, Preferred and Maximum values, the autorouter will use the Preferred value.
The Altium Designer rules system is hierarchical. The idea is that you start with a default rule for all objects, then add additional rules to selectively target other objects which have different requirements. For example, you should have a default rule for the routing width which covers the most common routing width used on the board, then add subsequent rules to selectively target other nets, classes of nets and so on.
To check that a rule is targeting the correct objects, copy the rule's Query into the PCB Filter panel and Apply it. Only those objects targeted by the rule should pass through the filter and remain displayed at full strength. Alternatively, use the PCB Rules And Violations panel to quickly see rule application across any defined rule for the current board.
The most important rules are the Width and Clearance rules. These routing technology settings define how tightly the routing can be 'packed'. Selecting these is a balancing process - the wider the tracks and bigger the clearance, the easier it is to fabricate the board; versus the narrower the tracks and clearances, the easier it is to route the board. It is advisable to consult your fabricator to establish their 'price points' for routing widths and clearances, those values which if you go below will result in lower fabrication yields and higher priced PCBs. As well as satisfying the electrical requirements of the design, the routing technology should also be chosen to suit the component technology, to allow each pin to be routed to.
The third rule that is part of the routing technology is the Routing Via Style. It should also be selected to suit the track and clearances being used, while considering the fabrication costs of the chosen hole size and annular ring.
You should also avoid excessive or unnecessary rules - the more rules, the more processing time, the slower the routing. Rules can be disabled if not required for autorouting.
Routing Width
Ensure there is a Width rule with a Query of All (a default rule), and that the Preferred setting is appropriate for the most common routing width you require. Make sure that this width, in combination with the appropriate clearance rule, allows all pads to be routed to. Configure additional routing width rules for nets that require wider or narrower routing.
If there are fine pitch components that have pins on nets with wider routing widths - for example, power nets - test route out from a power pin and also route out the pin on either side to ensure that it is physically possible to route these pins.
Clearance Constraint
Check for special clearance requirements, such as fine pitch components whose pads are closer than the standard board clearances. These can be catered for using a suitably scoped and prioritized design rule. Note that while you can define a rule to target a footprint, it will not target the routing that connects to that footprint. As just mentioned in the Routing Width section, test route to ensure that the component pins are routable.
Routing Via Style
Ensure there is a Routing Via Style rule with a Query of All and that the preferred setting is appropriate. Include higher priority rules for those nets that need a different via style than the default rule.
Altium Designer supports blind and buried vias, when these will be used is determined by the layer swaps allowed by the Via Types defined in the Layer Stack Manager (Design » Layer Stack Manager). Like interactive routing, when the autorouter switches between two layers it checks the current Via Type definitions - if these layers are defined as a blind or buried layer pair then the via that is placed will have these layers as its start and end layers. It is important to understand the restrictions to using blind/buried vias; they should only be used in consultation with your fabricator. As well as the restrictions imposed by the fabrication stackup technology, there are also reliability and testing accessibility considerations. Some designers consider it better to add more routing layers than to use blind/buried vias.
Routing Layers
Ensure there is a Routing Layers rule with a query of All. All enabled signal layers (defined in the layer stack) will be listed. Enable the layers upon which you wish to allow routing as required. Include higher priority rules for nets that you want to have routed on specific layers only.
Should you wish to exclude a particular net (or class of nets) from being routed by the autorouter, define a Routing Layer rule targeting that net or net class and, in the Constraints region for that rule, ensure that the Allow Routing option for each enabled signal layer is disabled. The priority for the rule must be higher than that of the default rule (the one with a query of All).
Layer Directions
Preferred routing directions are specified in the Layer Directions dialog, which is accessed from the Situs Routing Strategies dialog. All enabled signal layers (defined in the layer stack) will be listed.
Choose appropriate layer directions to suit the flow of the connection lines. Situs uses topological mapping to define routing paths, so it is not constrained to route horizontally and vertically. Typically it is best to have outer layers as horizontal and vertical. If, however, you have a multi-layer board with a large number of connections at a '2 O'clock' angle, then set one or more internal layers to have this as the preferred routing direction. The Layer Patterns pass in particular makes use of this information, and choosing the right direction can make a significant difference to routing performance in terms of both time and quality. Note that when you use angled layers you do not need to have a partner layer running at 90 degrees to this layer, since the router will typically route horizontally or vertically if it needs to avoid an obstacle on an angled layer.
Avoid using the Any direction - the layer that is chosen to route a connection on is based on how closely the connection is aligned with the layer direction, so this layer becomes the layer of last resort. The Any direction is typically only used on single-sided boards.
The Layer Directions dialog
Options and Controls of the Layer Directions Dialog
The dialog presents a grid listing each signal layer as defined in the layer stack. Each layer is presented in terms of the following:
- Layer - the name of the signal layer.
- Current Setting - the currently chosen preferred routing direction for the layer. This field is editable. Use the drop-down to select from the following options: Not Used, Horizontal, Vertical, Any, 1 O'Clock, 2 O'Clock, 4 O'Clock, 5 O'Clock, 45 Up, 45 Down, Fan Out, and Automatic.
- Actual Direction - the direction for routing that Situs is actually using. This field is read-only. It will follow the preferred routing direction chosen for the layer in the Current Setting field, unless Automatic is chosen, in which case it will calculate the best direction to be used, based on the defined routing directions for other layers.
Routing Priority
Use the Routing Priority rules to set a higher priority on difficult nets, or those that you want to have the cleanest routing.
SMD Fanout Control
The query system includes keywords that specifically target the different surface mount component packages including IsLCC (Leadless Chip Carrier), IsSOIC (Small Outline IC), and IsBGA (Ball Grid Array). Default rules are automatically created for the most common packages and since fanout passes are run early in the autorouting process, there is little penalty in keeping rules that do not apply to any components. You should have at least one SMD fanout control design rule if there are surface mount components on the board - a suitable query for a single rule targeting all surface mount components would be IsSMTComponent. For information on how each query keyword identifies a component package, open the Query Helper, type in the required keyword and press F1 .
The fanout rules include settings that control if the pads are to be fanned in or out, or a mixture of both. To help become familiar with the behavior of the Fanout Control rule attributes, the Route » Fanout » Component command can be run on any surface mount component that has no nets assigned to it. As well as using this to check how well a component fans out with the current routing technology defined in the board, you can also use it to fan out a component that you want to keep in a library as a pre-fanned out footprint. Once it is fanned out in the PCB workspace, copy and paste the component and the fanout tracks and vias into a library.
Rule Priorities
The precedence, or priority, of rules is defined by the designer. The rule priority is used to determine which rule to apply when an object is covered by more than one rule. If the priority is not set correctly, you may find that a rule is not being applied at all.
For example, if the rule with a query of InNet('VCC') has a lower priority than the rule with a query of All, then the All rule will be applied to the VCC net. Use the Priorities button in the PCB Rules and Constraints Editor dialog to access the Edit Rule Priorities dialog, from where priorities can be refined as necessary. Note that priority is not important when two rule scopes do not overlap (do not target the same objects). For example, it makes no difference which of these two rule scopes has a higher priority - InNet('VCC') or InNet('GND').
The Golden Rule
The most important step is to perform a design rule check (DRC) prior to starting the autorouter. When using the Route » Auto Route » Setup, or Route » Auto Route » All commands, Situs conducts its own pre-routing analysis and presents the results as a report in the Situs Routing Strategies dialog. From the dialog, you can interrogate the report for the design and choose the strategy to be used when routing. The routing strategy is the intelligence of the Router, defining which of the various routing algorithms to use and when in order to turn the 'virtual' routing paths identified in the topological map into high-quality, highly efficient, real routing on the board.
Make sure that the Routing Setup Report is clean before starting the autorouter.
The report provides information including:
- Design rules currently defined for the design that will be adhered to by the autorouter (and the number of design objects - nets, components, pads - affected by each rule)
- Routing directions defined for all signal routing layers
- Drill layer pair definitions
The report lists potential problems that could affect router performance. Where possible, hints are provided in order to advise in the better preparation of the design for autorouting. Any errors/warnings/hints that are listed should be scrutinized and, if needed, the corresponding routing rules adjusted, before proceeding to route the design.
Check all errors, warnings and hints to understand what potential problems the autorouter will face.
It is essential that any routing-related rule violations are resolved before starting the autorouter. Not only can violations prevent routing at the location of the violation, they can also greatly slow the router as it continually attempts to route an unrouteable area.
Notes on Running the Situs AutoRouter
Summary of the Routing Passes and Routing Strategies
Currently defined routing strategies are listed in the lower region of the Situs Routing Strategies dialog. Click the Add button to access the Situs Strategy Editor dialog, from where you can specify the passes to be included in a new strategy. Alternatively, use the Duplicate button to duplicate an existing strategy, and then edit it as required. The inclusion of various routing passes and the order in which they are used constitutes the Autorouter's 'intelligence'. These passes are used to turn the virtual routing paths identified in the topological map, into high-quality routes on the board.
A defined routing strategy and the constituent routing passes contained therein, are only applied when routing the entire board.
Example of editing a duplicated strategy.
Options and Controls of the Situs Routing Strategies Dialog
The dialog's controls are divided into two main regions. The only difference in controls between the two access methods is the button at the bottom of the dialog left of the Cancel button. When accessing to perform setup only (not route), this appears as the standard OK button. Clicking this will save changes to user-defined routing strategies. When accessing to route the entire board, it appears as the Route All button. Clicking this will attempt to route the board in accordance with the currently selected routing strategy.
Routing Setup Report
- Report Window - this area presents a report based on pre-routing analysis of the design, gathering together information including: Design rules currently defined for the design that will be adhered to by the Autorouter (and the number of design objects - nets, components, pads - affected by each rule), routing directions defined for all signal routing layers, and drill layer pair definitions.
The report lists potential problems that could affect router performance. These warnings can include routing layers that have their routing direction set to Any. Where possible, hints are provided in order to help in the better preparation of the design for autorouting. Any errors/warnings/hints that are listed should be scrutinized and, if needed, the corresponding routing rules adjusted before proceeding to route the design.
It is essential that any routing-related rule violations are resolved before starting the Autorouter. Not only can violations prevent routing at the location of the violation, they can also greatly slow the Autorouter as it continually attempts to route an unrouteable area.
Use hyperlink entries in the report to quickly access the Edit PCB Rule dialog for a given rule definition to adjust the scope and/or constraints of that rule as required. For unroutable pads, clicking the relevant hyperlink entry in the report will zoom and center the offending pad in the design space.
- Edit Layer Directions - click this button to access the Layer Directions dialog in which you can modify the routing directions for signal layers as required.
- Edit Rules - click this button to access the main PCB Rules and Constraints Editor dialog. Alternatively, if you want to modify an existing routing rule directly, click on the rule's respective hyperlink within the main body of the report.
- Save Report As - click this button to save the report as a HTML document. A standard Save As dialog will appear. By default, the report will be saved in the same location and with the same name as the PCB design file (DesignName.htm). Use the dialog to change the name and location as required.
Routing Strategy
- Available Routing Strategies - this area lists all of the currently available routing strategies that can be used by the Autorouter to route the design. Each strategy is listed in terms of its name and a description. The following six routing strategies are defined, and available by default:
- Cleanup - default cleanup strategy.
- Default 2 Layer Board - default strategy for routing two-layer boards.
- Default 2 Layer With Edge Connectors - default strategy for routing two-layer boards with edge connectors.
- Default Multi Layer Board - default strategy for routing multi-layer boards.
- General Orthogonal - default general purpose orthogonal strategy.
- Via Miser - default strategy for routing multi-layer boards with aggressive via minimization.
In general, the default routing strategies for two layer and multi-layer boards are fine for most routing situations. It is important, however, to ensure that any relevant routing design rules are set up prior to running the Autorouter.
- Add - click this button to add a new user-defined routing strategy to the list. The Situs Strategy Editor dialog will open in which you can fully define the strategy including, most importantly, its constituent routing passes.
- Remove - click this button to remove the currently selected and user-defined routing strategy from the list of available routing strategies.
The six default routing strategies cannot be removed.
- Edit - click this button to edit the currently selected and user-defined routing strategy. The Situs Strategy Editor dialog will open in which you can make changes to the strategy including its constituent routing passes, as required.
The six default routing strategies cannot be edited.
- Duplicate - click this button to make a duplicate of the currently selected routing strategy. The Situs Strategy Editor dialog will open. Give the new strategy its own, more meaningful name and description and modify its setup as required.
- Lock All Pre-routes - enable this option to prevent any pre-routed nets from being deleted ("ripped up") and re-routed by the Autorouter. Often, certain nets will be manually routed and then the remainder autorouted.
- Rip-up Violations After Routing - enable this option to have any routes that violate defined (and applicable) design rules ripped up after the Autorouter completes its routing session.
Options and Controls of the Situs Strategy Editor Dialog
Options
- Strategy Name - the current name for the strategy. If creating a new routing strategy, this field will contain the default entry New Strategy. Edit this field to give a more meaningful name as required.
- Strategy Description - the current description for the strategy. Enter a meaningful description that summarizes the purpose or scope of the strategy.
- More/Less Vias - use this slider bar to define permitted via usage by the Autorouter. This is a trade-off between greater routing speed and the use of fewer vias. Moving the bar to the right will constrain the Autorouter to place fewer vias, however, the time taken to route the board will be greater. Moving the bar to the left achieves faster routing completion times, however, at the expense of extra vias placed by the Autorouter on the PCB.
- Orthogonal - enable this option to constrain the Autorouter to routing orthogonal (90°) paths only. Disabling this option allows the Autorouter to route orthogonally or non-orthogonally (45°) as it sees fit.
Routing Passes
- Available Routing Passes - this area lists the available routing passes (algorithms) that can be used in a routing strategy. The following passes are available:
- Adjacent Memory - this is a connection-level routing pass. It is used to route adjacent same-net pins requiring fan-out with a simple U pattern.
- Clean Pad Entries - this is a connection-level routing pass. It reroutes out from each pad center along the longest axis of the pad.
For designs that include components with pads that have different X and Y dimensions, always include a Clean Pad Entries pass after the Memory pass.
- Completion - this is a connection-level routing pass. It is essentially the same as the Main pass, costed differently to resolve conflicts and complete difficult connections. Examples of costing differences include vias being cheaper and wrong-way routes being dearer.
- Fan out Signal - this is a component-level pass, based on the fanout settings defined by the Fanout Control. It checks for patterns in pads, considers clearance, routing width and via style, then selects a suitable fan out arrangement (inline row, staggered, etc.) to meet the requirements defined in the design rule. Fanout is to signal layers only.
- Fan out to Plane - this is a component-level pass, based on the fanout settings defined by the Fanout Control. It checks for patterns in pads, considers clearance, routing width and via style, then selects a suitable fan out arrangement (inline row, staggered, etc.) to meet the requirements defined in the design rule. Fanout is to an internal plane layer only.
- Globally Optimised Main - this is a connection-level routing pass. It provides optimal routing. It ignores contentions/violations on its first iteration. It then reroutes connections, with increased conflict costs, until there are no violations remaining. This pass, used in conjunction with the Orthogonal option enabled, can produce nicely routed patterns. Add a Recorner pass to the strategy to provide mitered cornering.
- Hug - this is a connection-level routing pass that reroutes each connection, following existing routing with the minimum clearance possible. The hug pass is used to maximize free routing space. Note that this pass is very slow.
- Layer Patterns - this is a connection-level routing pass. It only routes connections that match a layer direction (within a tolerance). It is costed to hug or follow existing routing to maximize free space.
- Main - this is a connection-level routing pass. It uses the topological map to find a routing path, then uses the push and shove router to convert the proposed path to actual routing.
- Memory - this is a connection-level routing pass. It checks for two pins on different components on the same layer that share X or Y coordinates.
- Multilayer Main - this is a connection-level routing pass. It is similar to the Main pass, but with costs optimized for multi-layer boards.
- Recorner - this is a connection-level routing pass that is used to provide mitering of routed corners. This pass is used when the Orthogonal option is enabled for the strategy - essentially overriding it and mitering the corners of each route. If the Orthogonal option is disabled for the strategy being used, there is no need to include a Recorner pass as the autorouter will miter corners by default.
- Spread - this is a connection-level routing pass that reroutes each connection, attempting to spread the routing to use free space and equally space routing when it passes between fixed objects (such as component pads). Note that this pass is very slow.
- Straighten - this is a connection-level routing pass that attempts to reduce the number of corners. It does this by walking along the route to a corner, then from that corner performs a (horizontal/vertical/45up/45down) probe searching for another routed point on the net. If one is found, it then checks to see if this new path reduces the routed length.
Only one main-type pass should be specified for a routing strategy - either Main, Multilayer Main or Globally Optimized Main.
- Passes in this Routing Strategy - this area lists the actual routing passes (algorithms) included in the strategy. You can add whatever passes you wish from the list of available passes and multiple instances of the same pass may be added throughout the overall strategy to achieve specific results. Passes will be executed, in order, from the top down. This order can be modified using the Move Up and Move Down buttons.
- Add - click this button to add the currently selected pass in the Available Routing Passes list to the Passes in this Routing Strategy list. The pass will be added above the currently selected pass in the latter.
- Remove - click this button to remove the currently selected pass in the Passes in this Routing Strategy list from the strategy.
- Move Up - click this button to move the currently selected pass in the Passes in this Routing Strategy list upward in the list. In other words, it will be used earlier in the routing strategy.
- Move Down - click this button to move the currently selected pass in the Passes in this Routing Strategy list downward in the list. In other words, it will be used later in the routing strategy.
User-defined strategies can be edited at any time, but the default strategies - Cleanup, Default 2 Layer Board, Default 2 Layer With Edge Connectors, Default Multi Layer Board, General Orthogonal, Via Miser - cannot be modified.
The following routing passes are available. The passes can be used in any order, as a guide examine an existing strategy to see the order of passes.
| PAss |
Function |
| Adjacent Memory |
A connection-level routing pass. It is used to route adjacent same-net pins requiring fan-out, with a simple U pattern. |
| Clean Pad Entries |
A connection level routing pass. It reroutes out from each pad center along the longest axis of the pad. If there are components with pads that have different X and Y dimensions, always include a Clean Pad Entries pass after the Memory pass. |
| Completion |
A connection level routing pass. It is essentially the same as the Main pass, costed differently to resolve conflicts and complete difficult connections. Examples of costing differences include vias being cheaper and wrong-way routes being dearer. |
| Fan Out Signal |
A component level pass, based on the fanout settings defined by the Fanout Control. It checks for patterns in pads, considers clearance, routing width and via style, then selects a suitable fan out arrangement (inline row, staggered, etc) to meet the requirements defined in the design rule. Fanout is to signal layers only. |
| Fan out to Plane |
A component level pass, based on the fanout settings defined by the Fanout Control. It checks for patterns in pads, considers clearance, routing width and via style, then selects a suitable fan out arrangement (inline row, staggered, etc) to meet the requirements defined in the design rule. Fanout is to an internal plane layer only. |
| Globally Optimized Main |
A connection level routing pass. It provides optimal routing. It ignores contentions/violations on its first iteration. It then reroutes connections, with increased conflict costs, until there are no violations remaining. This pass, used in conjunction with the Orthogonal option enabled, can produce nicely routed patterns. Add a Recorner pass to the strategy to provide mitered cornering. |
| Hug |
A connection level routing pass that reroutes each connection, following existing routing with the minimum clearance possible. The hug pass is used to maximize free routing space. Note that this pass is very slow. |
| Layer Patterns |
A connection level routing pass. It only routes connections that match a layer direction (within a tolerance). It is costed to hug or follow existing routing to maximize free space. |
| Main |
A connection level routing pass. It uses the topological map to find a routing path, then uses the push and shove router to convert the proposed path to actual routing. Only one main-type pass should be specified for a routing strategy - either Main, Multilayer Main, or Globally Optimized Main. |
| Memory |
A connection level routing pass. It checks for two pins on different components on the same layer that share X or Y coordinates. |
| Multilayer Main |
A connection level routing pass. It is similar to the Main pass, but with costs optimized for multilayer boards. |
| Recorner |
A connection level routing pass that is used to provide mitering of routed corners. This pass is used when the Orthogonal option is enabled for the strategy - essentially overriding it and mitering the corners of each route. If the Orthogonal option is disabled for the strategy being used, there is no need to include a Recorner pass as the autorouter will miter corners by default. |
| Spread |
A connection level routing pass that reroutes each connection, attempting to spread the routing to use free space and equally space routing when it passes between fixed objects (such as component pads). Note that this pass is very slow. |
| Straighten |
A connection level routing pass that attempts to reduce the number of corners. It does this by walking along the route to a corner, then from that corner performs a (horizontal/vertical/45up/45down) probe searching for another routed point on the net. If one is found, it then checks to see if this new path reduces the routed length. |
See Also
