在Altium Designer中验证电路板设计

The PCB editor is a rules-driven design environment in which you can define many types of design constraints that can be checked to ensure the integrity of your board. The online DRC feature monitors the enabled rules as you work and immediately highlights any detected design violations. Alternatively, you can also run a batch DRC to test that the design complies with the rules and generate a report that details the enabled rules and any detected violations.

Earlier in the tutorial, you examined and configured some design constraints, including electrical clearance, routing width, and routing via style. As well as these, there are a number of other design rules that are automatically defined when a new board is created.

Configuring and Running a Design Rule Check (DRC)

Main page: Setting Up & Running a DRC

The design is checked for violations by running the design rule check (DRC). Both online and batch DRC are configured in the Design Rule Checker dialog accessed by selecting the Tools » Design Rule Check command from the main menus. The dialog provides general reporting options (Report Options – ) and the ability to configure testing of specific rule types (Rules to Check – ).

A design rule check is run by clicking the  button at the bottom of the dialog. The DRC runs, and then the Messages panel opens and lists all detected violations. If the Create Report File option has been enabled in the dialog, a Design Rule Verification Report will open in a separate document tab. The report details the rules that are enabled for checking, the number of detected violations, and specific details about each violation.

1. Select the Tools » Design Rule Check command from the main menus to open the Design Rule Checker dialog.

2. On the Report Options page of the dialog, make sure that the Create Report File option is enabled.

   

3. On the Rules To Check page of the dialog, right-click in the grid area and select the Batch DRC - Used On entry.

   

4. Disable batch DRC for the testpoint rules. To do this, select the Testpoint section in the tree and disable the Batch checkboxes for the four rule types in this category.

   

5. Click the button at the bottom of the dialog to run DRC. The Design Rule Checker dialog will close and the report will open. It will include (at least):

   • 4 Minimum Solder Mask Sliver violations – the minimum width of a strip of solder mask is less than the allowed value.

   • 4 Clearance Constraint violations – the measured electrical clearance value between objects on signal layers is less than the specified minimum amount.

   
   The upper section of the report details the rules that are enabled for checking and the number of detected violations. Click on a rule to jump to and examine those violations.

   
   The lower section of the report shows each rule that is being violated, followed by a list of the offending objects. Click on a violation entry to jump to that object on the PCB.

   Detected violations will also be listed in the Messages panel that opens. 

   

Locating and Resolving Violations

Main page: Interrogating & Resolving Design Violations

As the designer, you have to locate a violation in the PCB, establish its condition and how much it has actually failed, and work out the most appropriate way of resolving the violation.

Resolving Clearance Violations

In the tutorial design, there are four violations of the Clearance constraint between pads of transistor footprints. There are two ways of resolving these violations:

• Decrease the size of the transistor footprint pads to increase the clearance between the pads, or

• Configure the constraint to allow a smaller clearance between the transistor footprint pads.

Since the 0.25 mm clearance is quite generous and the actual clearance is quite close to this value (0.22 mm), a good choice in this situation would be to configure the rules to allow a smaller clearance. This solution is acceptable in this situation because the only other component with thru-hole pads is the connector, which has pads spaced 1 mm apart. If this was not the case, the best solution would be to add a second clearance constraint targeting just the transistor pads, as was done for the solder mask expansion rules.

Resolving Minimum Solder Mask Sliver Violations

The solder mask is a thin, lacquer-like layer applied to the outer surface of the board, providing a protective and insulating covering for the copper. Openings are created in the mask for components and wires to be soldered to the copper. It is these openings that are displayed as objects on the solder mask layer in the PCB editor (note that the solder mask layer is defined in the negative – the objects you see become holes in the actual solder mask).

During fabrication, solder mask is applied using different techniques. The lowest cost approach is to silkscreen it onto the board surface through a mask. To allow for layer alignment issues, the mask openings are typically larger than the pads, reflected by the 4 mil (~0.1 mm) expansion value used in the default design rule.

There are other techniques for applying solder mask, which offer higher-quality layer registration and more accurate shape definition. If these techniques are used, the solder mask expansion can be smaller or even zero. Reducing the mask opening reduces the chance of having solder mask slivers or silk to solder mask clearance violations.

A solder mask sliver violation. The purple represents the solder mask expansion around each pad.

Violations such as these solder mask issues cannot be resolved without consideration of the fabrication technique that will be used to make the finished board.

For example, if this was a complex, multi-layer board for a high-value product, then it is likely that a high-quality solder mask technology would be employed, which would allow a small or zero solder mask expansion. However, a simple, double-sided board like the board in this tutorial is more likely to be fabricated as a low-cost product, requiring a low-cost solder mask technology to be used. That means resolving the solder mask sliver violations by reducing the solder mask expansion for the entire board is not an appropriate solution.

Like many aspects of PCB design, the solution lies in making thoughtful trade-offs in a focused way to minimize their impact.

To resolve this violation, you can:

• Increase the solder mask opening to completely remove the mask between the transistor pads, or

• Decrease the minimum acceptable sliver width, or

• Decrease the mask opening to widen the sliver to an acceptable width.

This is a design decision that would be made in light of your knowledge of the component and the fabrication and assembly technology that is going to be used. Opening the mask to completely remove the sliver of mask between the transistor pads means that there is more chance of creating solder bridges between those pads, whereas decreasing the mask opening will still leave a sliver, which may or may not be acceptable, and will also introduce the possibility of mask-to-pad registration problems.

For this tutorial, you will do a combination of the second and third options, decreasing the minimum sliver width to a value suitable for the settings being used on this board, and also decreasing the mask expansion, but only for the transistor pads.

Running a Design Rule Check After Resolving the Violations

Now, rerun the DRC to make sure that all violations have been resolved.

1. Open the Design Rule Checker dialog (Tools » Design Rule Check) and ensure that the Create Report File option is enabled on the Report Options page.

2. Click  the button.

3. A new report will be generated and opened in a separate document tab. Make sure that it does not contain any rule violations.

   

   If there are violations, resolve them, then generate the report again.

4. Remove the generated DRC report from the project. It will be generated during the design release process. To do this, find the report file under the Generated\Documents entry in the Projects panel, right-click on it and select the Remove from Project command. In the Remove from project dialog that opens, choose the Delete file option.

   

5. Close all documents that are currently open. You can do this by right-clicking a document tab at the top of the design space and selecting the Close All Documents command from the context menu.

6. Save the project to the Workspace. To do this, click the Save to Server control next to the project entry in the Projects panel, enter a meaningful comment into the Comment field of the Save to Server dialog that opens (e.g., PCB design complete), then click the OK button.