The PCB editor is a rules-driven design environment in which you can define many types of design constraints that can be checked to ensure the integrity of your board. The online DRC feature monitors the enabled rules as you work and immediately highlights any detected design violations. Alternatively, you can also run a batch DRC to test that the design complies with the rules and generate a report that details the enabled rules and any detected violations.
Earlier in the tutorial, you examined and configured some design constraints, including electrical clearance, routing width, and routing via style. As well as these, there are a number of other design rules that are automatically defined when a new board is created.
Configuring and Running a Design Rule Check (DRC)
Main page: Setting Up & Running a DRC
The design is checked for violations by running the design rule check (DRC). Both online and batch DRC are configured in the Design Rule Checker dialog accessed by selecting the Tools » Design Rule Check command from the main menus. The dialog provides general reporting options (Report Options – 
) and the ability to configure testing of specific rule types (Rules to Check – 
).
A design rule check is run by clicking the 
button at the bottom of the dialog. The DRC runs, and then the Messages panel opens and lists all detected violations. If the Create Report File option has been enabled in the dialog, a Design Rule Verification Report will open in a separate document tab. The report details the rules that are enabled for checking, the number of detected violations, and specific details about each violation.
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Select the Tools » Design Rule Check command from the main menus to open the Design Rule Checker dialog.
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On the Report Options page of the dialog, make sure that the Create Report File option is enabled.
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On the Rules To Check page of the dialog, right-click in the grid area and select the Batch DRC - Used On entry.
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Disable batch DRC for the testpoint rules. To do this, select the Testpoint section in the tree and disable the Batch checkboxes for the four rule types in this category.
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Click the button at the bottom of the dialog to run DRC. The Design Rule Checker dialog will close and the report will open. It will include (at least):
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4 Minimum Solder Mask Sliver violations – the minimum width of a strip of solder mask is less than the allowed value.
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4 Clearance Constraint violations – the measured electrical clearance value between objects on signal layers is less than the specified minimum amount.
The upper section of the report details the rules that are enabled for checking and the number of detected violations. Click on a rule to jump to and examine those violations.
The lower section of the report shows each rule that is being violated, followed by a list of the offending objects. Click on a violation entry to jump to that object on the PCB.
Detected violations will also be listed in the Messages panel that opens.
Locating and Resolving Violations
Main page: Interrogating & Resolving Design Violations
As the designer, you have to locate a violation in the PCB, establish its condition and how much it has actually failed, and work out the most appropriate way of resolving the violation.
Notes on Locating and Resolving Violations
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Altium Designer has two techniques for displaying design rule violations:
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Violation overlay – violations are identified by indicating the offending primitive using a pattern (by default, green circles with crosses).
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Violation details – the nature of violations are detailed using a numerical value that shows the constraint that is failing and/or an icon that indicates the site and type of violation.
An example of a Clearance violation is shown below. Both of the above techniques are used to indicate the violation. Offending pads are highlighted using a pattern. Also, the violation is indicated by the white arrows and the <0.25mm text, indicating that this gap is less than the minimum 0.25 mm allowed by the constraint.
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To locate a violation, click the link in the report file's lower section that details specific violations or double-click an entry in the Messages panel.
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Violation entries in the report and Messages panel also include details on how much a violation has failed. The actual value is detailed along with the specified constraint value (for example, 0.017mm < 0.254mm).
Resolving Clearance Violations
In the tutorial design, there are four violations of the Clearance constraint between pads of transistor footprints. There are two ways of resolving these violations:
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Decrease the size of the transistor footprint pads to increase the clearance between the pads, or
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Configure the constraint to allow a smaller clearance between the transistor footprint pads.
Since the 0.25 mm clearance is quite generous and the actual clearance is quite close to this value (0.22 mm), a good choice in this situation would be to configure the rules to allow a smaller clearance. This solution is acceptable in this situation because the only other component with thru-hole pads is the connector, which has pads spaced 1 mm apart. If this was not the case, the best solution would be to add a second clearance constraint targeting just the transistor pads, as was done for the solder mask expansion rules.
Do I have the Constraint Manager or the PCB Rules and Constraints Editor dialog?
Depending on whether the Constraint Manager or the PCB Rules and Constraints Editor dialog is available for the tutorial design (you can quickly check by opening the Design main menu from the PCB editor when the project's PCB document is open and checking for the Constraint Manager or Rules command), use the corresponding approach described in one of the collapsible sections below.
Resolving Clearance Violations (Constraint Manager)
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Click the PCB document tab at the top of the design space to make it the active document.
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Select the Design » Constraint Manager command from the main menus to open the Constraint Manager.
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On the Clearances view of the Constraint Manager, click within the All Nets / All Nets cell in the clearance matrix.
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Change the TH Pad – to – TH Pad value to 0.22 mm in the grid region at the bottom. To do this, click the cell, type in 0.22, and press Enter.
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Javascript ID: Tutorial_CM_Clearance
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Save changes in the Constraint Manager (File » Save to PCB).
Resolving Clearance Violations (PCB Rules and Constraints Editor Dialog)
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Click the PCB document tab at the top of the design space to make it the active document.
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Open the PCB Rules and Constraints Editor dialog (Design » Rules).
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Locate and select the existing Clearance rule in the Electrical category on the left of the dialog.
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Change the TH Pad – to – TH Pad value to 0.22 mm in the grid region of the rule constraint. To do this, click the cell, type in 0.22, and press Enter.
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Javascript ID: Tutorial_Dlg_PCBRulesAndConstraintsEditor_Clearance_AD24
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Click Apply to accept the changes and keep the PCB Rules and Constraints Editor open.
Resolving Minimum Solder Mask Sliver Violations
The solder mask is a thin, lacquer-like layer applied to the outer surface of the board, providing a protective and insulating covering for the copper. Openings are created in the mask for components and wires to be soldered to the copper. It is these openings that are displayed as objects on the solder mask layer in the PCB editor (note that the solder mask layer is defined in the negative – the objects you see become holes in the actual solder mask).
During fabrication, solder mask is applied using different techniques. The lowest cost approach is to silkscreen it onto the board surface through a mask. To allow for layer alignment issues, the mask openings are typically larger than the pads, reflected by the 4 mil (~0.1 mm) expansion value used in the default design rule.
There are other techniques for applying solder mask, which offer higher-quality layer registration and more accurate shape definition. If these techniques are used, the solder mask expansion can be smaller or even zero. Reducing the mask opening reduces the chance of having solder mask slivers or silk to solder mask clearance violations.
A solder mask sliver violation. The purple represents the solder mask expansion around each pad.
To see details of minimum solder mask sliver violations details, the display of the solder mask must be enabled. Use the View Configuration panel to configure layer visibility.
Violations such as these solder mask issues cannot be resolved without consideration of the fabrication technique that will be used to make the finished board.
For example, if this was a complex, multi-layer board for a high-value product, then it is likely that a high-quality solder mask technology would be employed, which would allow a small or zero solder mask expansion. However, a simple, double-sided board like the board in this tutorial is more likely to be fabricated as a low-cost product, requiring a low-cost solder mask technology to be used. That means resolving the solder mask sliver violations by reducing the solder mask expansion for the entire board is not an appropriate solution.
Like many aspects of PCB design, the solution lies in making thoughtful trade-offs in a focused way to minimize their impact.
To resolve this violation, you can:
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Increase the solder mask opening to completely remove the mask between the transistor pads, or
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Decrease the minimum acceptable sliver width, or
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Decrease the mask opening to widen the sliver to an acceptable width.
This is a design decision that would be made in light of your knowledge of the component and the fabrication and assembly technology that is going to be used. Opening the mask to completely remove the sliver of mask between the transistor pads means that there is more chance of creating solder bridges between those pads, whereas decreasing the mask opening will still leave a sliver, which may or may not be acceptable, and will also introduce the possibility of mask-to-pad registration problems.
For this tutorial, you will do a combination of the second and third options, decreasing the minimum sliver width to a value suitable for the settings being used on this board, and also decreasing the mask expansion, but only for the transistor pads.
Do I have the Constraint Manager or the PCB Rules and Constraints Editor dialog?
Depending on whether the Constraint Manager or the PCB Rules and Constraints Editor dialog is available for the tutorial design (you can quickly check by opening the Design main menu from the PCB editor when the project's PCB document is open and checking for the Constraint Manager or Rules command), use the corresponding approach described in one of the collapsible sections below.
Resolving Solder Mask Sliver Violations (Constraint Manager)
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The first step is to reduce the allowable sliver width. Open the All Rules view of the Constraint Manager by clicking the corresponding button at the top of the Constraint Manager.
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In the left-hand side tree, locate and select the Solder Mask Sliver rule type in the Manufacturing category, then select the existing rule called MinimumSolderMaskSliver in the main grid area.
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A value equal to the pad separation of 0.22 mm (~8.7 mil) will be acceptable for a design such as this. Edit the Minimum Solder Mask Sliver value to be 0.22 in the constraint region of the rule.
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The next step is to add a mask expansion rule for just the transistors that reduces the mask expansion to zero. Doing this will mean that the opening in the solder mask is the same size as the pad, making the width of solder mask sliver between the pads equal to the separation distance between the pads (0.22 mm). Click on the Solder Mask Expansion rule type in the Mask category of the left-hand side tree to show the existing rules of this type. There should be one rule called SolderMaskExpansion which specifies an expansion value of 0.1016 mm (4 mil).
Since it is only the transistor pads that are in violation, you will not edit this value. Instead, you will create a new rule.
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To add a new Solder Mask Expansion rule, right-click in a free space of the main grid area and select Add Custom Rule from the context menu. A new rule called SolderMaskExpansion_1 will be created.
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Double-click the name of the new rule in the main grid area and type in SolderMaskExpansion_Transistor to change its name.
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Click on the rule to display its settings in the bottom part of the Constraint Manager.
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Define the scope of the new rule. A scope query can be created using the Query Builder feature. Click the 
button next to the Object Match field and select the Open Query Builder command. In the Building Query from Board dialog that opens, select Associated with Footprint from the drop-down in the Condition Type / Operator column, then select ONSC-TO-92-3-29-11 from the drop-down in the Condition Value column. After clicking OK in the dialog, the query (HasFootprint('ONSC-TO-92-3-29-11')) will appear in the Object Match field.
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Javascript ID: Tutorial_CM_SolderMaskExpansion_New_Query_AD24
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Set 0 for Expansion top and Expansion bottom values.
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Save changes in the Constraint Manager (File » Save to PCB).
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Close the Constraint Manager by right-clicking its tab at the top of the design space and selecting the Close Multivibrator.PcbDoc [Constraints] command from the context menu.
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Save the PCB document locally by right-clicking its entry in the Projects panel and selecting Save from the context menu.
Resolving Solder Mask Sliver Violations (PCB Rules and Constraints Editor Dialog)
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The first step is to reduce the allowable sliver width. To do this, locate and select the existing Minimum Solder Mask Sliver rule called MinimumSolderMaskSliver in the Manufacturing category of the left-hand side tree in the PCB Rules and Constraints Editor dialog.
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A value equal to the pad separation of 0.22 mm (~8.7 mil) will be acceptable for a design such as this. Edit the Minimum Solder Mask Sliver value to be 0.22 in the Constraints region of the rule.
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The next step is to add a mask expansion rule for just the transistors that reduces the mask expansion to zero. Doing this will mean that the opening in the solder mask is the same size as the pad, making the width of solder mask sliver between the pads equal to the separation distance between the pads (0.22 mm). Expand the Mask category of the left-hand side tree, then expand the Solder Mask Expansion rule type. There should be one rule called SolderMaskExpansion.
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Click on the rule to select it and display its settings. It will specify an expansion value of 0.102mm (4 mil).
Since it is only the transistor pads that are in violation, you will not edit this value. Instead, you will create a new rule.
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To add a new Solder Mask Expansion rule, right-click on the existing rule in the tree on the left and select New Rule from the context menu.
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A new rule called SolderMaskExpansion_1 will be created. Click on it to display its settings.
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Edit the rule settings to be as shown below:
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Name – SolderMaskExpansion_Transistor.
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Where the Object Matches – select Footprint in the drop-down, then select ONSC-TO-92-3-29-11 (the name of the transistor footprint) in the second drop-down that appears.
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Expansion top / Expansion bottom – 0.
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Click OK to accept the changes and close the PCB Rules and Constraints Editor dialog.
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Save the PCB document locally by right-clicking its entry in the Projects panel and selecting Save from the context menu.
Running a Design Rule Check After Resolving the Violations
Now, rerun the DRC to make sure that all violations have been resolved.
Always confirm that you have a clean Design Rule Verification Report before generating outputs.
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Open the Design Rule Checker dialog (Tools » Design Rule Check) and ensure that the Create Report File option is enabled on the Report Options page.
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Click the button.
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A new report will be generated and opened in a separate document tab. Make sure that it does not contain any rule violations.
If there are violations, resolve them, then generate the report again.
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Remove the generated DRC report from the project. It will be generated during the design release process. To do this, find the report file under the Generated\Documents entry in the Projects panel, right-click on it and select the Remove from Project command. In the Remove from project dialog that opens, choose the Delete file option.
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Close all documents that are currently open. You can do this by right-clicking a document tab at the top of the design space and selecting the Close All Documents command from the context menu.
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Save the project to the Workspace. To do this, click the Save to Server control next to the project entry in the Projects panel, enter a meaningful comment into the Comment field of the Save to Server dialog that opens (e.g., PCB design complete), then click the OK button.
Well done! You have confirmed that the PCB complies with the constraints and are ready to
create the PCB drawing.
