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Documentation Altium Designer Documentation ... Dialog Reference A to F

Electrical Rules Check Setup

Created: July 28, 2015 | Updated: March 01, 2018 | Applies to versions: 15.1, 16.0, 16.1, 17.0, 17.1, 18.0 and 18.1
Now reading version 16.0. For the latest, read: Electrical Rules Check Setup for version 22

  

                                         The Columns, Error Reporting, and Connection Matrix tabs of the Electrical Rules Check Setup dialogThe Columns, Error Reporting, and Connection Matrix tabs of the Electrical Rules Check Setup dialog

Summary

The Electrical Rules Check Setup dialog allows you to configure the ERC.

Using validation reports defined in an assigned Output Job file provides the ability to validate your designs as an integral part of its board design release process. These validation checks will be performed on every release, and the release will fail if any validation checks are not passed successfully. This gives you additional peace of mind that costly errors do not creep in to your released designs due to last minute changes. Validation is run at the Validate Design stage of the process flow within the PCB Release view. In Design Mode, the validation checks are performed directly on your project, before outputs are generated. In Release Mode, the release flow first builds a self-contained snapshot from your project that includes all project documents and external dependencies, and the validation checks are performed on this snapshot. This provides additional security that the snapshot has correctly captured all the required dependencies for your project.

Access

The dialog is accessed using the following steps:

  1. Open an OutJob file.
  2. Click Add New Validation Output under Validation Outputs.
  3. Select Electrical Rules Check from the drop-down.
  4. Select desired schematic document from the resulting drop-down.
  5. Right-click in the newly-added Electrical Rules Check entry then click Configure.

Options/Controls

The chosen settings can be stricter or more lenient than the settings defined in the Project Options for your project. You can reset the settings of your Electrical Rules Check to the same as your Project Options by clicking the Set To Project Default button.

Columns Tab

  • Validation - use the drop-down to define the maximum tolerated error level when using the ERC output generator as part of validation during the board design release process. The validation stage of the release process flow (in either Design or Release modes) uses the checking defined in the Output Job only and not the project-level ERC checking. In this way, you can define an even more restrictive/rigid set of checks to be passed, in turn ensuring even higher integrity of the design data. Options include:  ,   ,  .      
  • Suppressed Errors - enable this option to report any suppressed errors.
  • Show Columns - choose which columns are to be displayed in ERC report. Options include Class, Document, and Message. As selections are made, the Preview region is updated to show column settings.
  • Preview - shows the current errors detected for the design, based on validation using the error checking defined on the tabs within the dialog. Change a checking level and the design is re-validated (recompiled) dynamically, and the preview region is updated. Use the options in the Show Columns region to toggle display of the corresponding columns within the preview area.

Error Reporting Tab

This tab enables you to define the reporting levels for each of the possible violations that can exist on source schematic documents when compiling the project. When the project is compiled, these violation settings will be used in conjunction with the Connection Matrix tab to test the source documents for violations. Any violations that are found that have a report level of Warning, Error, or Fatal Error will be displayed as violation messages in the Messages panel. In addition, if compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler Preferences page of the Preferences dialog), an offending object will display a colored squiggle beneath it.

Violations Grid

This region presents all possible violations that can exist on the source documents of the project. Violations themselves are gathered into the following categories:

Each specific violation type is presented with the following fields:

  • Violation Type Description - a short description of the type of violation.
  • Report Mode - use this field to specify the severity level associated with violating the check. Use the drop-down to choose from the following reporting levels:

Right-Click Menu

The following commands are available from the right-click menu:

  • All Off - set the Report Mode for all violation types to No Report.
  • All Warning - set the Report Mode for all violation types to Warning.
  • All Error - set the Report Mode for all violation types to Error.
  • All Fatal - set the Report Mode for all violation types to Fatal Error.
  • Default - set the Report Mode for all violation types back to their default settings.
Multiple violation types can be selected using standard multi-select techniques (Ctrl+click, Shift+click).

Notes

  • Use the Connection Matrix tab to specify reporting levels associated with electrical violations concerning pins, ports and sheet entries specifically.
  • There may be points in the design that you know will be flagged as electrical violations that you do not want to be flagged. To suppress these, place a No ERC schematic design directive object at those points.
  • Generally, it is better to first compile the design and examine the warnings with the default settings. For those warnings that are not an issue for the current design, the reporting level can be changed.

Connection Matrix Tab

This tab displays a matrix that provides a mechanism to establish connectivity rules between component pins and net identifiers, such as Ports and Sheet Entries. It defines the logical or electrical conditions that are to be reported as warnings or errors. For example, an output pin connected to another output pin would normally be regarded as an error condition, but two connected passive pins would not.

When the project is compiled, these violation settings will be used in conjunction with the defined settings on the Error Reporting tab to test the source documents for violations. Any violations that are found and have a report level of Warning, Error, or Fatal Error will be displayed as violation messages in the Messages panel. In addition, if compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it.

Matrix

The matrix presents all possible wiring connection checks, between combinations of pins, ports, and sheet entries, as well as testing for unconnected entities. The matrix is read in an across/down fashion and the color of the matrix element at the row-column intersection specifies how the compiler will respond when testing for that particular condition.

To change the reporting mode for a violation check in the matrix, simply click on the colored square where the row and column of two entities intersect. Each time you click, the mode will move to the next report level. The following levels are supported:

As you hover over a square, text is displayed below the matrix to describe the violation and the reporting mode.

Right-Click Menu

The following commands are available from the right-click menu:

  • All Off - set all entries in the matrix to No Report.
  • All Warning - set all entries in the matrix to Warning.
  • All Error - set all entries in the matrix to Error.
  • All Fatal - set all entries in the matrix to Fatal Error.
  • Default - set all entries in the matrix back to their default settings.

Notes

  • Use the Error Reporting tab to specify reporting levels associated with further electrical and drafting violations.
  • There may be points in the design that you know will be flagged as electrical violations that you do not want to be flagged. To suppress these, place a No ERC schematic design directive object at those points.

Additional Controls

  • Set To Project Default - click to return all settings to the same as your Project Options.
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