Ensuring Design Integrity with Design Rule Checking (DRC) in Altium Designer
Design Rule Checking (DRC) is a powerful automated feature that checks both the logical and physical integrity of a design. Checks are made against any or all enabled Design Rules and can be made online in real-time as you design or as a batch process, with results listed in the software's Messages panel and a (optional) generated report.
This feature should be used on every routed board to confirm that minimum clearance rules have been maintained and that there are no other design violations. It is particularly recommended that a batch mode design rule check always be performed prior to generating final artwork.
To learn more about setting up and running a Design Rule Check for your PCB, refer to the Setting Up & Running a DRC page.
To learn more about interrogating and resolving design violations detected during a Design Rule Check, refer to the Interrogating & Resolving Design Violations page.
DRC Validation in an Output Job
Altium Designer provides the ability to define and run a DRC validation report as part of an Output Job Configuration file (*.OutJob). With an OutJob file open as the active document, the report is available from the Validation Outputs grouping of outputs. To add a report, click the [Add New Validation Output] control and choose the Design Rules Check entry and select the PCB document as the source.
Add a DRC validation report to an Output Job file.
Validation as Part of PCB Design Release
Using validation reports defined in an assigned Output Job file, the software provides the ability to validate designs as an integral part of its design release process. These validation checks will be performed on every release, and the release will fail if any validation checks are not passed successfully. Validation is run at the Validate Project stage within the Release view with results available at the Review Data stage.
Example of successful validation being run within the Release view, for fabrication and assembly data sets.