PCB_Dlg-ViaStitching_FloodOptionsFormAdd Stitching to Net_AD

The Add Stitching to Net dialog 

Summary

The Add Stitching to Net dialog provides controls to configure stitching settings for the design, including stitching parameters and via style. Via stitching is run as a post-process, filling free areas of copper with stitching vias. For via stitching to occur, there must be overlapping regions of copper that are attached to the specified net on different layers. Supported regions of copper include Fills, Polygons and Power Planes.

Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure and helping maintain a low impedance and short return loops. In RF designs stitching is used in combination with guard rings to create a via wall, helping create an electromagnetically 'quiet' PCB. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net to that net.

Using the selected net, the stitching algorithm identifies all Fills, Polygons and Power Planes attached to that net and attempts to connect them through the board, using the specified via and stitching pattern.  

The via stitching algorithm treats Polygons, Fills and Planes in the following way:

• Polygons and Fills that are on the same net are stitched wherever they overlap on different layers. If there are Polygons or Fills on other nets that are overlapping within that area (on another layer), stitching is not applied in that region. Overlapping Plane regions on other nets are passed through.
• Overlapping Plane regions on the target net are always stitched, regardless of the presence of Plane regions (on another layer) attached to other nets. Rule 1 above applies if there are Polygons or Fills overlapping in the same region.

Access

The dialog is accessed in the PCB Editor by clicking Tools » Via Stitching/Shielding » Add Stitching to Net from the main menus.

Options/Controls

Stitching Parameters

The stitching parameters control the stitching vias' placement pattern and their clearance from other-net and same-net objects.

• Constrain Area - enable to constrain via stitching to a specific area. After selecting the option, you will be taken to the design space. After using the cross-hair cursor to define the constrain area, right-click to return to the dialog.
• Edit Area - click to edit the constrain area.
• Offset - enter the X and Y offset distance(s).
• Grid - the distance between the center of adjacent stitching vias. Stitching vias will not be placed in violation of applicable design rules; if a potential via site would result in a violation that site is skipped.    
• Stagger alternate rows - alternate rows of shielding vias are offset by half of the Grid value.  

Same Net Clearances

There are two ways of controlling the clearance of stitching vias to vias and pads on the same net: either the applicable Clearance design rule is used or the Default Via/Pad Clearance specified here is used. If a rule exists, the tighter of these settings is used. These options behave as follows:

• Create new clearance rule - a stitching via-versus-other via/pad design rule is created when this button is clicked. This rule setting is used to ensure a potential stitching site is valid. When clicked, the PCB Rules and Constraints Editor dialog opens in which the rule Constraints can be set. Note that the rule is named and scoped to target the net selected in the dialog.
• Edit Clearance Rule - if an applicable design rule already exists, this button will be present instead of the Create New Clearance Rule button. Click to change the Constraint rule settings. 
• Default Via/Pad Clearance - stitching vias are only placed on potential stitching sites if this much clearance exists. Since potential stitching sites are determined by the stitching grid, it is likely they will be further than apart than this setting.  
• Min Boundary Clearance - stitching vias are only placed on potential stitching sites if this much clearance exists to the edge of Polygon/Fill/Plane regions. 

Via Style

The stitching Via Style can be configured manually or imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. Clicking this button will load the Preferred rule settings. 

Diameters

• Simple - Via Style(Hole size and diameter) is the same through all layers.
  • Hole size - specify the hole size value for the Via.
  • Tolerance Min/Max - setting hole tolerance attributes can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
  • Diameter - specify the diameter for the Via.

• Top-Middle-Bottom - different Hole Size and Diameters can be set at Top Layer, Middle Layer and Bottom Layer respectively.
  • Hole size - specify the hole size value for the Via.
  • Tolerance Min/Max - setting hole tolerance attributes can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
  • Top Layer - specify via size for top layer.
  • Middle Layer - specify via size for Middle layer.
  • Bottom Layer - specify via size for Bottom layer.

• Full Stack - different Hole Size and Diameters can be edited at each layer(including all signal layers and planes).
  • Hole size - specify the hole size value for the Via.
  • Tolerance Min/Max - setting hole tolerance attributes can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
  • Edit Full Stack Via Sizes - click to open the Via Layer Editor dialog in which you can specify via settings for each layer stack.

Via Template

• Template - select a via template from the dropdown.
• Library - displays to which library the via template is linked and includes the option to Unlink the template from said library.

Properties

• Drill Pair - the layers on which this via starts and ends.
• Net - the net to which the via is currently assigned. Change the net assignment by clicking in the field and choosing a net from the drop down list. Select No Net to specify that the via is not connected to any net. The Net property of a primitive is used by the Design Rule Checker to determine if a PCB object is legally placed.
• Locked - enable this option to protect the via from being edited graphically. Lock a via whose position is critical. If you try to edit a primitive that is locked, you will be informed that the primitive is locked and asked if you want to proceed with the action. If this option is unchecked, the primitive can be freely edited without confirmation.

Solder Mask Expansions

• Expansion value from rules - enable this option to allow the existing solder mask expansion rule to take effect on this pad object. Check the Mask design category from the PCB Rules and Constraints Editor dialog.
• Specify expansion value - enable this option to edit the expansion value and the solder mask expansion design rule is overridden for this pad.
• Force complete tenting on top - enable to override any solder mask settings in the solder mask expansion design rules which results in no opening in the solder mask on top layer of this pad. 
  Disable this option and this pad is affected by a solder mask expansion rule or specific expansion value.
• Force complete tenting on bottom - enable to override any solder mask settings in the solder mask expansion design rules which results in no opening in the solder mask on the bottom layer of this pad. Disable this option and this pad is affected by a solder mask expansion rule or specific expansion value.

Additional Controls

• Via Types - click to open the Layer Stack Manager in which you can configure the via types for the active layer stack.

Tips

• Once stitching is complete, you will need to re-pour the polygons if the applicable Polygon Connect Style design rule specifies a relief connection style.
• Each set of stitching vias are added to a union. The set can be removed by running the Tools » Via Stitching » Remove Via Stitching Group command, then clicking on any via in the group.