Performing Design Updates to Your Captured Multi-board System in Altium NEXUS

Parent page: Capturing the Logical System Design

During the course of a multi-board system design, it’s likely that the source child projects will also be developed, and those changes need to be brought into (synchronized with) the system design. This update process is achieved by re-importing the child design(s) into the Multi-board design space via an Engineering Change Order (ECO).

Use the Design » Import From Child Projects command to import changes from all Child Projects in the system design, or the Design » Import From Selected Child Projects alternative to re-import the connection data for the project modules that are currently selected in the workspace. These commands are also available from the right-click Design context menu of a Module graphic.

The executed ECO will register any differences between the current system design connectivity and the connection data that has been imported from the child project(s). This information is available in the Connection Manager dialog (Design » Connection Manager), which is also used to resolve or reject the updated connection data from the Child Project(s).

Resolve Conflicts

The Connection Manager dialog listing will highlight any connections that are considered as in Conflict, or in practice, any imported connection update that does not agree with the system design editor’s existing connectivity data map. Select a highlighted Net entry in the list to see a graphic representation of the Conflict and to access a range of button options that can be used to resolve it.

The Net information shown in the highlighted fields in the Connection Manager listing represents the proposed change. In the example case shown here, the Nets on HDR1 pins 4 and 5 in the Child Project (LCD Module) are in a different order – in fact, they have been swapped.

The Connection Manager will interpret this change and offer appropriate correction action buttons on the Conflict Resolution graphic. The options include:

• Confirm – The Nets on Pins 4 and 5 for the HDR1 connector in Module M2 will be changed in the system design to match the updated assignments (as highlighted) in the dialog.
• Revert – The current Net to Pin relationship for HDR1 in Module M2 will be retained. The proposed change is ignored by the system design. Note that the system design will then not match the net assignments in the child design(s).
• Swap Pins – The Pin/Net assignments at the other end of the connection (at HDR6 on M1, the main board PCB) will be changed to maintain a correct Net relationship between the two Modules (M1 and M2).
• Swap Wires - The virtual wires that connect between HDR1 on M2 and HDR6 on M1 will be changed (swapped in this case) to correct the Net connectivity conflict, and the connector Pin/Net assignments will not be changed. Here, wire W2 would then connect between Pin 4 on HDR6 and Pin 5 on HDR1, and W3 connect between Pins HDR6-5 and HDR1-4.

When a conflict resolution option has been selected, an affirmative answer in the following Confirmation dialog will cause the conflict resolution action to be applied to all conflicts of the same type.

The corrected Net assignments will be highlighted in green and also reflected in the dialog's lower connection graphic. Select the button to apply the updated assignments to the Multi-board system design.

Once the Conflict Resolution changes have been applied, they can be inspected in the Properties panel when the relevant connection is selected in the system design workspace.

In the Properties panel image shown below, the example conflict for the W-LCD connection was resolved using the Swap Wires option. This has effectively crossed over wires W2 and W3 so that the correct Net continuity is maintained, i.e the Reset and Read/Write Nets are matched between project Modules (LCD_RW# → RSW and LCD_RS# → RS, respectively).

Update Child Projects

To maintain synchronization between a multi-board schematic design and the child PCB projects it includes, the system designer supports the bidirectional exchange of Pin/Net data. Connectivity data is imported into the system design from child projects as outlined above, and the system design connectivity data may be passed back to the source PCB projects through the child project Update feature (Design » Update Child Projects). To update an individual child project, select its associated Module and choose the Design » Update Selected Child Projects command – both commands are also available on a Module's right-click Design context menu.

When the command is run, the design editor compares the connectivity data in the system design with that in the child projects. Any differences that are detected will be listed as proposed changes in a following Engineering Change Order (ECO) dialog, or a Comparator alert dialog will indicate that no differences have been encountered – and by implication, that no changes are required to maintain the system design to child project synchronization.

For the differences detected in the example shown here, where the RS and RSW Nets have been swapped on connector HDR1 in the LCD Board Child Project (M2 in the system design), the ECO proposes a Pin Swap in the source project to synchronize the Nets.

When the ECO is executed (after optional validation), the HDR1 connector Pins in the LCD module Child Project are swapped.

Note that the Update Child Projects process would normally be performed after any conflicts have been resolved in the Connection Manager dialog, so as to synchronize the child projects to the correct state of the system design.

In the above example, the child project Pin/Net relationship has been restored to the state prior to its changes. This is equivalent to where the changed child project data has been imported into the system design, and the connection conflict was been resolved using the Revert option. If the Swap Pins option was used to resolve the conflict, Pins 4 and 5 on the HDR6 connector in the main board project would have been swapped.

Other detected and resolved changes, such as a mismatched Net name are synchronized by a direct update to the target in the child project.