WorkspaceManager_Dlg-AnsysEDBExportOptionsAnsys EDB Export Options_AD

This document is no longer available beyond version 21.0. Information can now be found here: Exporting the PCB in ANSYS EDB Format for version 25

 

Summary

The Ansys EDB Export Options dialog is used to configure what is to be included when exporting Ansys EDB files.

Access

The dialog is accessed from the PCB editor by selecting File » Export » Ansys EDB.

Options/Controls

Component Types

  • Resistors - enter the resistor component value that is mapped to the property for RLC components in the Ansys component model that you want to be included in the export process.
  • Capacitors - enter the capacitor component value that is mapped to the property for RLC components in the Ansys component model that you want to be included in the export process.
  • Inductors - enter the inductor component value that is mapped to the property for RLC components in the Ansys component model that you want to be included in the export process.
  • Integrated Circuits - enter the integrated circuit component value that is mapped to the property for RLC components in the Ansys component model that you want to be included in the export process.
  • Input/Output - enter the input/output component value that is mapped to the property for RLC components in the Ansys component model that you want to be included in the export process.
The component type (resistor, capacitor, inductor) is deduced from the component's designator prefix, R - resistor, L - inductor, C- capacitor. Components with any other designator prefix are assigned the Part Type property value of Other in ANSYS. The component value is mapped to the R, L or C property for RLC components in the ANSYS component model. This can be accessed through the Model Info button in ANSYS

Units

Select either Imperial or Metric to be used as the preferred unit of measurement during export.

Others

Merge Net Tie Nets - when enabled, if a design contains nets connected by Net-Tie components, these nets will report as distinguished single nets in the netlist.

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참고

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