Working with the Undershoot - Falling Edge Design Rule on a PCB in Altium Designer

Created: 3月 23, 2017 | Updated: 9月 26, 2019 | Applies to versions: 18.0, 18.1, 19.0, 19.1, 20.0, 20.1 and 20.2

現在、バージョン 18.0. をご覧頂いています。最新情報については、バージョン Working with the Undershoot - Falling Edge Design Rule on a PCB in Altium Designer の 21 をご覧ください。

注記

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ソフトウェアの機能が見つからない場合は、Altium の営業担当者に連絡して詳細を確認してください。

Rule category: Signal Integrity

Rule classification: Unary

Summary Copy Link Copied

This rule specifies the maximum allowable undershoot (ringing above the base value) on the falling edge of the signal.

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.

Constraints Copy Link Copied

Default constraints for the Undershoot - Falling Edge rule.

Maximum (Volts) - the value for the maximum permissible undershoot on the falling edge of the signal.

How Duplicate Rule Contentions are Resolved Copy Link Copied

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application Copy Link Copied

Batch DRC and during Signal Integrity analysis.

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