PCB_Dlg-ViaPropertiesVia_AD

The Via dialog.

Summary

The Via dialog allows the designer to edit the properties of a Via. A via is used to create vertical connections between the signal layers of a PCB. A via has a hole, that once it is plated, creates this vertical connectivity. Vias can span all layers in the board design, or can start and stop at specific layers. Note that these types of vias can only be designed in conjunction with the board fabricator, as they must have the appropriate processes and technology to create vias between the specified layers.

Access

This dialog can be accessed during placement by pressing the Tab key.

After placement, the dialog can be accessed in the following ways:

• Double-click on the placed object.
• Place the cursor over the object, right-click and choose Properties from the context menu.

Options/Controls

Via Template

• Template - Select a Via template from the dropdown.
• Library - Displays which library the via template is linked to and includes the option to unlink the template from said library.

Diameters

• Simple - The via Diameter is the same on all layers.
• Top-Middle-Bottom - Different Diameters can be set for the: Top Layer, all internal signal layers, and Bottom Layer respectively.
  • Top Layer - Specify the via diameter for the Top Layer.
  • Middle Layer - Specify the via diameter for the Middle layers (all internal signal layers).
  • Bottom Layer - Specify the via diameter for the Bottom layer.
• Full Stack -
  • Edit Full Stack Via Sizes - Click to open the Via Layer Editor dialog which provides controls related to pad/via diameter for each layer. View the dialog page for more information. Note that the same dialog is used for both pads and vias, for a via, it will only have the diameter option.

• Hole size - The size of the hole in the via.
• Tolerance - Setting the hole tolerance attribute can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
• Location X/Y - The X and Y coordinates of the via.
• Diameter - Specify the diameter of the via.

Properties

• Drill Pair - The layers that this via starts and ends on.
• Net - The net that the via is currently assigned to. Change the net assignment by clicking in the field and choosing a net from the drop down list. Select No Net to specify that the via is not connected to any net. The Net property of a primitive is used by the Design Rule Checker to determine if a PCB object is legally placed.
• Locked - Enable this option to protect the via from being edited graphically. Lock a via whose position is critical. If you try to edit a primitive that is locked, you will be informed that the primitive is locked and asked if you wish to proceed with the action. If this option is unchecked, the primitive can be freely edited without confirmation.

Testpoint Settings

Use the Testpoint Settings to define this via as a testpoint for Fabrication and/or Assembly testpoint file generation. A testpoint is a location where a test probe can make contact with the PCB to check for correct function of the board. Any via can be nominated as a testpoint.

• Top - Enable this option for this via to be defined as a top layer testpoint.
• Bottom - Enable this option for this via to be defined as a bottom layer testpoint.

Solder Mask Expansions

An opening in the solder mask is automatically created by the software, the same shape as the via. This opening can be larger (a positive expansion value) or smaller (a negative expansion value) than the via itself, as defined by the Solder Mask Expansion setting. The expansion is measured from the edge of the copper.

• Expansion value from rules - When this option is enabled the solder mask expansion for this via is defined by the applicable Solder Mask Expansion design rule. The Solder Mask Expansion design rule is defined on the Mask - Solder Mask for Expansion pages of the PCB Rules and Constraints Editor dialog.
• Specify expansion value - Enable this option to override the rule and specify the solder mask expansion value for this via.
• Solder Mask From Hole Edge - If the expansion value is being specified here in the Via dialog, then you can also enable this option to define the solder mask expansion from the edge of the hole, instead of the edge of the via.
• Force complete tenting on top - The term tenting means to close off. If this option is enabled then the settings in the applicable solder mask expansion design rule will be overridden, resulting in no opening in the solder mask on the top solder mask layer for this via. When this option is enabled, the Expansion value from rules and the Specify expansion value options are ignored.
• Force complete tenting on bottom - The term tenting means to close off. If this option is enabled then the settings in the applicable solder mask expansion design rule will be overridden, resulting in no opening in the solder mask on the bottom solder mask layer for this via. When this option is enabled, the Expansion value from rules and the Specify expansion value options are ignored.

Tenting

Partial and complete tenting of vias can also be achieved by defining an appropriate value for Solder Mask Expansion. This expansion constraint can either be defined on a via-by-via basis in the associated Via dialog, or by defining appropriate Solder Mask Expansion design rules. By setting the expansion value to a suitable value, you can achieve the following:

• To partially tent a via - covering the land area only, set the Expansion to a negative value that will close the mask right up to the via hole.
• To completely tent a via - covering the land and hole, set the Expansion to a negative value equal to or greater than the via radius.
• To tent all vias on a single layer, set the appropriate Expansion value and ensure that the scope (Full Query) of a Solder Mask Expansion rule targets all vias on the required layer.
• To completely tent all vias in a design, in which varying via sizes are defined, set the Expansion to a negative value equal to or greater than the largest via radius. When tenting an individual via, options are available to follow the expansion defined in the applicable design rule, or to override the rule and apply a specified expansion directly to the individual via in question.