Error Reporting Options for a Project in Altium Designer

  The Error Reporting tab of the Project Options dialog for Multi-board project (back image) and a PCB project (front image)

Summary

This tab of the Project Options dialog enables you to define the reporting levels for each of the possible electrical and drafting violations that can exist on source schematic documents when compiling the project. When the project is compiled, these violation settings will be used in conjunction with the settings on the Connection Matrix tab to test the source documents for violations.

Any violations that are found that have a report level of Warning, Error or Fatal Error will be displayed as violation messages in the Messages panel. In addition, if compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it.

Access

This is one of multiple tabs available when configuring the options for a project accessed from within the Project Options dialog. To access this dialog:

• Click Project » Project Options in the Schematic or PCB Editor.
• Right-click on the Project entry on the Projects panel then click Project Options from the context menu.

Options/Controls

Violations List

This list presents all possible electrical and drafting violations that can exist on the source documents of the project. Violations themselves are gathered into the following categories:

• Violations Associated with Buses
• Violations Associated with Components
• Violations Associated with Connections (available for multi-board projects only)
• Violations Associated with Documents
• Violations Associated with Harnesses
• Violations Associated with Mated Parts  (available for multi-board projects only)
• Violations Associated with Nets
• Violations Associated with Others
• Violations Associated with Parameters

Each specific violation type is presented with the following fields:

• Violation Type Description - a short description of the type of violation.
• Report Mode - use this field to specify the severity level associated with violating the check. Use the drop-down to choose from the following reporting levels:
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Right-Click Menu

The following commands are available from the right-click menu:

• All Off - set the Report Mode for all violation types to No Report.
• All Warning - set the Report Mode for all violation types to Warning.
• All Error - set the Report Mode for all violation types to Error.
• All Fatal - set the Report Mode for all violation types to Fatal Error.
• Selected Off - set the Report Mode for all selected violation types to No Report.
• Selected To Warning - set the Report Mode for all selected violation types to Warning.
• Selected To Error - set the Report Mode for all selected violation types to Error.
• Selected To Fatal - set the Report Mode for all selected violation types to Fatal Error.
• Default - set the Report Mode for all violation types back to their default settings.

Additional Options

• Report Suppressed Violations in Messages Panel - enable this option to display violations in the Messages panel even if they have been suppressed through this tab.

Tips

• Use the Project Options - Connection Matrix tab to specify reporting levels associated with electrical violations concerning pins, ports and sheet entries specifically.
• There may be points in the design that you know will be flagged as electrical violations that you do not want to be flagged. To suppress these, place a No ERC schematic design directive object at each point.
• Generally, it is better to first compile the design and examine the warnings with the default settings. For those warnings that are not an issue for the current design, the reporting level can be changed.

• One option of interest is Nets with only one pin. This can be used to detect single node nets where a pin has been connected to a Port for example, but does not connect to another pin. This is set to Error by default and can be changed to No Report if the single node net is intentional.