Search In: Doc:Documentation: Altium Designer
Altium DesignerAltium 365Altium MCAD CoDesignerAltium On-Prem Enterprise ServerCompany Dashboard
Ver: Version: 18.1
2120.220.120.019.119.018.118.017.117.016.116.015.1
Close
搜索 Search on Documentation

Project Compiler Violations Reference_AD

Created: 九月 22, 2017 | Updated: 九月 22, 2017 | Applies to versions: 18.0, 18.1, 19.0 and 19.1
您正在阅读的是 18.1. 版本。关于最新版本，请前往 ((Project Compiler Violations Reference))_AD 阅读 21 版本
注

软件的功能取决于您购买的Altium产品级别。您可以比较Altium Designer软件订阅的各个级别中包含的功能，以及通过Altium 365平台提供的应用程序所能实现的功能。

如果您在软件中找不到某个讨论过的功能，请联系Altium销售团队以获取更多信息。

The process of compiling is integral to producing a valid netlist for a project. In fact it is the process of compilation that yields the unified data model of a design - the single model of the data that is accessible across the design domains in Altium Designer's unified design environment. Connectivity awareness in your schematic diagram can be verified during compilation according to rules defined as part of the options for the design project - on the Error Reporting and Connection Matrix tabs respectively.

This area of the Altium Designer documentation provides a comprehensive reference describing each of the possible electrical and drafting violations that can exist in source documents when compiling a project.

For a detailed overview of verifying your captured design, see Compiling and Verifying the Design.

Violations are grouped into the following categories:

中文(简体)
If you find an issue, select the text/image and pressCtrl + Enterto send us your feedback.
适合打印版本
注

软件的功能取决于您购买的Altium产品级别。您可以比较Altium Designer软件订阅的各个级别中包含的功能，以及通过Altium 365平台提供的应用程序所能实现的功能。

如果您在软件中找不到某个讨论过的功能，请联系Altium销售团队以获取更多信息。