Компиляция и верификация проекта

Parent page: Embarking on Your Next Design Project

The Unified Data Model and Compiling the Design

A fundamental element of the software is the Unified Data Model (UDM). Data within the model can be accessed and manipulated by the various editors and services within the software including the schematic and the PCB. Rather than using a separate data store for each of the various design domains, the UDM is structured to accommodate all information from all aspects of the design, including the components and their connectivity.

The Unified Data Model makes all of the design data available to all of the editors and helps deliver sophisticated design features, like multi-channel design and variants.

This single, cohesive model that sits central to the design process is created as a result of dynamic design compilation. It means that the Unified Data Model is available from the moment a project is opened and should not require additional manual compilation – a true Dynamic Data Model (DDM). Therefore, the model is incrementally updated (compiled) after each user operation. You can freely place, wire, rearrange, rename, add, and delete content from your schematic design.

The design compilation process is managed by code outside of the schematic and PCB editors. There are a number of advantages to this approach, with the biggest being that the Unified Data Model of the design sits outside of the individual schematic and PCB editors. The UDM includes detailed descriptions of every component in the design and how they connect to each other.

The software manages the connective data across the schematic and the PCB.

The following locations and operations do not require any additional manual actions in terms of design compilation as compilation is dynamic:

• Navigator and Projects panel
• ActiveBOM
• Performing ECO
• Cross-probing
• Net color highlighting
• Pin swapping
• Component cross reference

So how do you interact with the Unified Data Model, for example, to trace a net through the design? You do that through the Navigator panel.

Examining the Connectivity in the Navigator Panel

Panel page: Navigator

If the design is large and spread over many sheets, it can become difficult to follow a net and verify the connectivity in the design by simply looking at the schematics. To help with this process, you can use the Navigator panel. The panel gives a view of the entire, validated design. The Navigator panel can be opened by clicking the Panels button at the bottom right of the design space then selecting Navigator.

To use the panel:

• Set the browsing behavior by clicking at the top of the panel to open the System – Navigation page of the Preferences dialog and enable the preferred Highlight Methods. Alternatively, right-click on the object of interest in the panel then use the context menu options to configure the navigation behavior.
• Set the scope of your browsing in the first section of the panel. To browse the entire design select Flattened Hierarchy.
• Click on a component in the Instance section of the list to jump to that component, expand the component to locate, or jump to a pin.

• Click on a net or bus in the Net / Bus section to jump to that net or bus, to expand the component to locate, or to jump to a pin.

  
  Click on a component or net in the Navigator panel to locate that component or net and trace the connectivity through the design. Right-click to access display options.

As is explained in this document, when you think it is ready, you can then validate your design.

Schematic Validation and Configuring the Verification Options

To validate your design, choose the Validate PCB Project <ProjectName> command from the main Project menu.

The software checks for logical, electrical, and drafting errors between the Unified Data Model and project checking settings.

There are a large number of drafting and electrical checks that can be performed on the validated design. These are configured as part of the project options. Select the Project » Project Options command from the main menus to open the Project Options dialog (shortcut: C, O). The default settings will not suit every design and, therefore, it is important to become familiar with the options and how to configure them to suit your design.

Drafting Checks

During validation, common drafting and editing errors are checked in accordance with the settings on the Error Reporting tab of the Project Options dialog.

The error checks are organized in groups, for example, Violations Associated with Nets, Violations Associated with Components, etc. The groups are listed alphabetically in the dialog.

The Report Mode of each violation can be changed to one of four values by clicking on it and selecting the desired value in the drop-down.

Generally, it is better to first validate the design and examine the warnings with the default settings. For those warnings that are not an issue for the current design, the reporting level can be changed.

One option of interest is Nets with only one pin. This can be used to detect single node nets where a pin has been connected to a Port or Net Label but does not connect to another pin. This is set to No Report by default and can be changed to Warning to help detect broken nets.

Connectivity Checks

The electrical connectivity is checked in accordance with the settings on the Connection Matrix tab of the Project Options dialog.

The matrix provides a mechanism to establish connectivity rules between component pins and net identifiers, such as Ports and Sheet Entries. It defines the logical or electrical conditions that are to be reported as warnings or errors. For example, an output pin connected to another output pin would normally be regarded as an error condition, but two connected passive pins would not.

Click on the small square in the matrix to change a particular rule. Each rule determines the reporting level for a given pin/net identifier combination. There are four possible values for each rule: Fatal Error, Error, Warning, and No Report.

Verifying the Components

Main page: Building & Maintaining Your Components and Libraries

A key aspect of verifying the design is to be confident that the components are correct. Typically this is done as the components are saved to your connected Workspace, through a Component Rule Check performed by the Component Validator.

The Component Validator tests for an array of potential issues with the component and its defined models – both hardwired tests, as well as a range of violation types that can be user-defined at the global level. Any violations that are found are listed in the Messages panel.

The following hardwired validation checks all carry a report mode of Fatal Error:

1. Component not referencing any models.
2. A target folder not specified for the component in the target Workspace.
3. Component not having a unique Id.

User-definable checks are configured on the Data Management – Component Rule Checks page of the Preferences dialog.

Any of the hardwired tests that fail, or user-defined checks at a level of Error or above, will prevent saving of the component to the Workspace.

Interpreting Messages and Locating Errors

Panel page: Messages

When the project is validated, every condition that generates a warning or error is listed in the Messages panel. Note that the Messages panel will only open automatically if there is at least one Error or Fatal Error condition. To check for a Warning, you will need to open the panel manually by clicking the Panels button on the bottom-right of the design space then choose Messages. Once the project has been validated, the panel will list any warnings and errors that have been detected.

The Messages panel displays the warnings and errors detected in the project.

The Messages panel is command central for presenting violations. Things to be aware of include:

• Nets with no driving source (Violations associated with Nets section) – if the net does not include a pin with the Electrical Type of Output or I/O, this error will occur. There are many valid situations that can cause this, for example, a net from a connector pin to an input pin.
• Nets with multiple names (Violations associated with Nets section) – if you change the name of a net (for example, you connect a named net to a sheet entry with a different name (which is permitted) because that sheet entry name better reflects the net's function on the lower-level child sheet), this error will occur. It also occurs in a multi-channel design where the software must assign a unique name to each repeated net.
• Component Revision has Inapplicable State (Violations associated with Components section) – this check results in the message Can't perform revision state validation. It occurs when there is a component that has been placed from a server and that server does not support revision state validation.
• The Messages panel has two regions – the upper grid region summarizes the warnings/errors; the lower region gives details of the currently selected warning/error.
• Double-click on a message to cross-probe to that warning/error. Double-click on a detail to show that specific object.
• You can click on any of the Messages panel column headings (e.g., Class, Document, Message) to assist in sorting the errors and warnings.
• Right-click in the Messages panel then use the appropriate Clear command to delete messages or use the Export To Report command to export the messages to a report.
• The panel includes warnings and errors detected from settings in both the Error Reporting tab and the Connection Matrix tab.
• When you right-click on a warning/error in the Messages panel then select the Place Specific No ERC for this violation command, you will automatically cross probe to the error location and a No ERC directive will appear on the cursor, ready to place on the error location. Press Tab to edit the properties of the directive prior to placement, if required:
  • As a generic directive, suppress all error checks at the point that the directive is placed.
  • As a specific directive, only suppress the specified error checks at the point that the directive is placed.

Resolving a Warning or Error

It is important to address each warning or error that is detected. The default error settings tend to be conservative since it is better for the software to err on the side of being cautious and let you decide if the testing boundaries can be relaxed. For example, your design may require IO pins to be connected to Input ports, requiring you to adjust the appropriate cell in the Connection Matrix tab. Another common error check to be changed is the Nets with no driving source, requiring you to disable that check in the Error Reporting tab.

There will be situations when you want to test the entire design for a certain condition, but you want to ignore a warning/error at a specific point in the circuit. For example, you might want to allow a net to be renamed at a specific location, but only in that location. This can be done by placing a No ERC directive at that location.

Using the No ERC Directive

Object page: No ERC

When you need to allow a specific point in the circuit to not report an error, place a No ERC (Electrical Rules Check) directive on that point (Place » Directives » Generic No ERC) meaning do not flag a warning/error at this location. Set the No ERC symbol style and color to suit its role in the circuit in the No ERC mode of the Properties panel.

Place No ERC directives to suppress warnings or errors at a specific location.

Note that No ERC directives can be excluded from printouts, if required, by enabling the relevant option(s) in the Print dialog.

No ERC directives can be excluded from schematic printouts by configuring related options in the Print dialog.

You can place a Specific No ERC directive directly at the error location from the Messages panel (right-click then choose Place Specific No ERC for this violation as shown in the images below) or at the violation.

The right-click command makes it easy to place a specific No ERC directive directly at the error location, either from the Messages panel or at the violation.

More about Violations

The software can test for a large number of potential error conditions. Information about each error check can be found using the links below.

• Violations Associated with Buses
• Violations Associated with Components
• Violations Associated with Connections (multi-board design projects only)
• Violations Associated with Documents
• Violations Associated with Harnesses
• Violations Associated with Mated Parts (multi-board design projects only)
• Violations Associated with Nets
• Violations Associated with Others
• Violations Associated with Parameters