Additional Options for a Project in Altium Designer

Created: Lipiec 28, 2015 | Updated: Sierpień 11, 2018 | Applies to versions: 15.1, 16.0, 16.1, 17.0 and 17.1

Now reading version 17.1. For the latest, read: Additional Options for a Project in Altium Designer for version 21

The Options tab of the Project Options dialog

Summary

This tab of the Project Options dialog enables you to specify the output path and related options for generated outputs for the project. You can also specify various netlisting options and the Net Identifier Scope.

Access

This is one of multiple tabs available when configuring the options for a project accessed from within the Options for Project dialog. To access this dialog:

Click Project » Project Options in the Schematic or PCB Editor.
Right-click on the Project entry on the Projects panel then click Project Options from the context menu.

Only the second method of access can be used for an Integrated Library project.

Options/Controls

When working with an Integrated Library project (*.LibPkg), the Options tab in the Options for Integrated Library dialog (a variation of the dialog described here) does not contain the following regions of controls: Netlist Options, Net Identifier Scope, and Allow Pin-Swapping Using These Methods.

Output Path - the default output path for generation of output files from the current design project (*.PrjPcb) or when compiling packaged libraries (*.LibPkg) as an integrated library.
ECO Log Path - the default output path for ECO log files.
Schematic Template Location - use this field to specify a directory in which to source schematic template files (*.SchDot, *.SchDoc) for the project.

Output Options

Open outputs after compile - enable to open files that were generated after compiling the design project.
Timestamp folder - enable to create a timestamp folder for generated output. The folder name is in the format <FolderName> Date Time where the <FolderName> is specified in the Output Path field and Date and Time are in the same format as your system settings.
Archive project document - enable to archive the project document.
Use separate folder for each output type - enable to create separate folders for each output type generated for the design project. If you have opted to create a timestamp folder, separate folders will be created under that folder.

Netlist Options

Allow Ports to Name Nets - enable to name a net using the Name property of a wired port rather than using a default, system-generated net name.
Allow Sheet Entries to Name Nets - enable to name a net using the sheet entry name rather than using a default, system-generated net name.
Allow Single Pin Nets - enable to allow the existence of nets containing only a single pin.
Append Sheet Numbers to Local Net - enable to append the value for a schematic document's Sheet Number parameter (a document-level parameter) to nets that are local to that sheet. A local net is a net that does not leave the sheet. For a net that does leave the sheet (and is therefore not local), this option does not apply.

If the Net Identifier Scope option is set to Global, then all nets with the same net label will be connected together on all sheets. Since these nets are not local, the Append Sheet Numbers to Local Net option is not applied.

The Append Sheet Numbers to Local Net option will only work if each schematic sheet has been assigned a unique SheetNumber. The SheetNumber parameter is assigned in the Parameters tab of the Document Options dialog for each schematic sheet. As an alternative to manually assigning a unique number to each schematic sheet, run the Number Schematic Sheets command, which opens the Sheet Numbering for Project dialog. This can be used to assign unique SheetNumbers (a simple numeric value for each sheet) and DocumentNumbers (typically used for a company-assigned document numbering), to all sheets.

Higher Level Names Take Priority - enable to have the net labels used on higher sheets in the hierarchy name the nets on the lower sheets.
Power Port Names Take Priority - the software has the ability to localize a global power net by wiring a power port to a normal port. This would force all pins on that sheet connected to that power port to be in a separate net. Enabling this option would force net naming using the name of the net assigned to the power port.

If only Higher Level Names Take Priority is enabled, the naming order of precedence is as follows: Net labels, power ports, ports, pins. However, if the Power Port Names Take Priority option is also enabled, then the naming order of precedence is: Power ports, net labels, ports, pins.

Net Identifier Scope

Multi-sheet designs are defined at the electrical (or connective) level by Net Identifiers. Net identifiers (net labels, ports, sheet entries, power ports, and hidden pins) create logical connections between points in the same net. This can be within a sheet or across multiple sheets. Physical connections exist when one object is attached directly to another electrical object by a wire. Logical connections are created when two net identifiers of the same type (e.g., two net labels) have the same Net property.

When the connectivity model of the design is created, you must define how you want net identifiers to connect to each other – this is known as setting the Net Identifier Scope. There are essentially two ways of connecting sheets in a multi-sheet design: either horizontally, directly from one sheet to another sheet to another sheet, etc., or vertically, from a sub-sheet to the sheet symbol that represents it on the parent sheet. In horizontal connectivity, the connections are from port to port (net label to net label is also available). In vertical connectivity, the connections are from sheet entry to port.

The scope of net identifiers should be determined at the beginning of the design process.

Use the drop-down list to choose from the following scopes:

Automatic (Based on project contents) - this mode automatically selects which of the net identifier modes to use based on the following criteria: if there are sheet entries on the top sheet, then Hierarchical is used; if there are no sheet entries, but there are ports present, then Flat is used; if there are no sheet entries and no ports, then Global is used.

The Automatic mode defaults to use the standard Hierarchical mode if need be, with power ports connecting globally. To use Strict Hierarchical, manually set the Net Identifier Scope accordingly. Hidden pins are always deemed to be global.

Flat (Only ports global) - ports connect globally across all sheets throughout the design. With this option, net labels are local to each sheet, i.e., they will not connect across sheets. All ports with the same name will be connected on all sheets. This option can be used for flat multi-sheet designs. It is not recommended for large designs as it can be difficult to trace a net through the sheets.
Hierarchical (Sheet entry <-> port connections, power ports global) - connect vertically between a port and the matching sheet entry. This option makes inter-sheet connections only through sheet symbol entries and matching sub-sheet ports. It uses ports on sheets to take nets or buses up to sheet entries in corresponding sheet symbols on the parent sheet. Ports without a matching sheet entry will not be connected even if a port with the same name exists on another sheet. Net labels are local to each sheet, i.e., they will not connect across sheets. However, power ports are global – all power ports with the same name are connected throughout the entire design. This option can be used to create designs of any depth or hierarchy and allows a net to be traced throughout a design on the printed schematic.
Strict Hierarchical (Sheet entry <-> port connections, power ports local) - this mode of connectivity behaves in the same way as the Hierarchical mode, with the only difference being that power ports are kept local to each sheet, i.e., they will not connect across sheets to power ports of the same name.
Global (Netlabels and ports global) - ports and net labels connect across all sheets throughout the design. With this option, all nets with the same net label will be connected together on all sheets. Also, all ports with the same name will be connected on all sheets. If a net connected to a port also has a net label, its net name will be the name of the net label. This option can also be used for flat multi-sheet designs, however, it is difficult to trace from one sheet to another since visually locating net names on the schematic is not always easy.

If the design uses sheet symbols with sheet entries, the Net Identifier Scope should be set to Hierarchical or Strict Hierarchical. In either of these modes, the top sheet must be wired. If not using sheet symbols with sheet entries, connectivity can be established via Ports and/or Net labels therefore one of the other two net identifier scopes (Flat or Global) should be used accordingly.

Remember that net labels do not connect to ports of the same name.

Allow Pin-Swapping Using These Methods

In the PCB editor, Pin, Differential Pair and Part swaps are performed by exchanging nets on component pads and their corresponding copper. When the changes are merged into the schematics, there are two ways that a pin swap can be handled:

Adding / Removing Net-Labels - enable to allow swapping of pins on a component symbol. Performing the swap on the schematic by swapping net labels can only be done if the connectivity is established through the net labels, that is, if the pins are not hardwired together.

The advantage of this approach is that the component symbol does not change and can be updated from the library at a later date. This approach is the best choice for a complex component, such as an FPGA, where physically moving two pins on the symbol could result in an I/O bank-based symbol presenting incorrectly.

Changing Schematic Pins - enable to allow swapping of net labels on the wires attached to the pins of a component. Swapping Pins will be the only option available when nets have been physically hardwired to a component. This method can be used on simple components (such as a resistor array) or where there is no alternative because of the structure of the schematic design.

Swapping the pins will always work on the schematic, but it may mean that the instance of the component symbol is no longer the same as it was defined in the library. In this situation, it means the symbol can no longer be updated from the library without destroying swapping information. It also means that other instances of the same component in this design will have a different pin arrangement, which could be a source of confusion to someone reading the schematic.

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