Project Compiler Violations Reference_AD

Now reading version 19.0. For the latest, read: ((Project Compiler Violations Reference))_AD for version 21

The process of compiling is integral to producing a valid netlist for a project. In fact it is the process of compilation that yields the unified data model of a design - the single model of the data that is accessible across the design domains in Altium Designer's unified design environment. Connectivity awareness in your schematic diagram can be verified during compilation according to rules defined as part of the options for the design project - on the Error Reporting and Connection Matrix tabs respectively.

This area of the Altium Designer documentation provides a comprehensive reference describing each of the possible electrical and drafting violations that can exist in source documents when compiling a project.

For a detailed overview of verifying your captured design, see Compiling and Verifying the Design.

Violations are grouped into the following categories:

If you find an issue, select the text/image and pressCtrl + Enterto send us your feedback.
참고

Altium 제품에 접근할 수 있는 레벨에 따라 사용할 수 있는 기능이 달라집니다. 다양한 레벨의 Altium Designer Software Subscription에 포함된 기능과 Altium 365 플랫폼에서 제공하는 애플리케이션을 통해 제공되는 기능을 비교해보세요.

소프트웨어에서 논의된 기능을 찾을 수 없는 경우, Altium 영업팀에 문의하여 자세한 정보를 확인해주세요.