Working with the Undershoot - Falling Edge Design Rule on a PCB in Altium Designer
Created: March 23, 2017 | Updated: September 26, 2019
| Applies to versions: 18.0, 18.1, 19.0, 19.1, 20.0, 20.1 and 20.2
Now reading version 20. For the latest, read: Working with the Undershoot - Falling Edge Design Rule on a PCB in Altium Designer for version 21
Rule category: Signal Integrity
Rule classification: Unary
Summary
This rule specifies the maximum allowable undershoot (ringing above the base value) on the falling edge of the signal.
Constraints
Default constraints for the Undershoot - Falling Edge rule.
- Maximum (Volts) - the value for the maximum permissible undershoot on the falling edge of the signal.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.
Rule Application
Batch DRC and during Signal Integrity analysis.