FpgaPinMapper_Dlg-PinMapperPin Mapper_AD

The Pin Mapper dialog

Summary

The Pin Mapper dialog allows you to create a link between an external pin file (such as one exported from FPGA or Microcontroller (MC) tools) with a schematic component then compare the pin signals between those two domains (FPGA and PCB).

Access

The dialog is accessed from the schematic editor by right-clicking on a placed component then choosing Pin Mapping from the context menu.

Options/Controls 

• Part Selection - allows the pins that are listed in the mapping table to be filtered by the selected part. You also can check for parts that are not placed in the schematic and parts that are not synced with the external FPGA file (displays a red indicator as shown below). 

• Component - if there are multiple component parts linked with the external file, use the controls to switch between options for this kind of component.
• Image - displays the footprint preview; the selected pins are highlighted and pins can be displayed by groups using the Preview mode drop-down.
• Preview mode - use the drop-down to select the desired preview mode. Choices include None, Bank Number, IO Pins, and Diff Pair Pins. The file name and path of the source FPGA/MC pin file is displayed below. Click  to browse to and select a pin file from a local drive. Only temporary Xilinx or Altera Pin files (*.csv) can be selected.
• Schematic - lists the Pin Designator and Net Name. Use the arrow next to the right of each column header name to sort the column in ascending/descending order. Click  in the column header to access a drop-down to filter the column contents. The following solution options are displayed for each pin: 
  • (Synced) - pin net names are synchronized, no changes are required.
  •   (Update Pin File) - transfer net name from the schematic to the external FPGA pin file (which is updated). Net names from the Schematic will be copied to the Signal names in the FPGA pin file; the source csv pin file is rewritten.
  • (Update Schematic) – change the schematic net name to match the Signal name in the external FPGA pin file (schematic is updated). Net labels in Schematic will change to match the source FPGA Signal names.
  • (Ignore) – reject changes, no updates will be performed.
  • (Warning) – there is a non-critical difference in pin name matching between the schematic and the external (FPGA) file. If desired, select an update option (or Ignore) from the drop-down menu.
• External - the Pin Table lists the source pin assignment. Pin assignment changes are displayed and can be and applied to the schematic component, or back.
• Export - click to start the workflow with an FPGA pin file from the schematic side and generate an Altium Pin Report file.
• Apply - click this button after choosing the appropriate action from the icon drop-down menu for each entry (row) in the table.

Right-click Menu

The grid tables include the following right-click menu commands:

• Update All pins in Schematic - choose to update all pin names in the schematic.
• Update All pins in Pin File -  choose to update all pin names in the pin file.
• Ignore for All pins - choose to ignore for all pins.
• Update Selected pins in Schematic - choose to update selected pin names in the schematic.
• Update Selected pins in Pin File - choose to update selected pin names in the pin file.
• Ignore for Selected pins - choose to ignore for selected pins.
• Default for All pins - choose to use the default for all pins.
• Default for Selected pins - choose to use the default for selected pins.

Tips

• Swapping must be defined manually by importing changes from the FPGA pin file data.
• Since the external pin file is linked to a component, a new component model (Pin Info) is created and shown in the Models list in the Component mode of the Properties panel. The panel's Models section also allows the pin info to removed or modified.
• When the component has model Pin Info, additional pin parameters and options will available for that component in the Configure Pin Swapping dialog