WorkspaceManager_Err-AddingHiddenNetToSheetAdding Hidden Net to Sheet_AD

Parent category: Violations Associated with Nets

Default report mode:

Summary

This violation occurs when there are two or more hidden pins within the project that have the same value entered into their Connect To field. Hidden pins are sometimes used to define the power pins in a multi-part component. Typically this warning occurs when a library component with hidden pins has been used and the designer was not aware of those hidden pins.

Notification

If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the Preferences dialog) an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:

Adding hidden net

Recommendation for Resolution

The problem arises when the following properties for the offending pin(s) are evident (in the associated Pin Properties dialog):

• The Hide option is enabled
• The Connect To field contains the specific power net name

If it is by design then the warning can be ignored. Alternatively you can enable the display of the pin(s) in the workspace (disable the Hide option in the Pin Properties dialog). This option may prove to be less than desirable, especially if you have many hidden pins connected to power nets. Revealing these pins in the workspace can cause clutter as each pin would need to be wired to the appropriate power port object - making the design schematic(s) less easy to read.

If you choose to display the hidden pins and those pins are assigned to Part Zero, they will appear on every part placed in the project. For multi-part component power pins that are not hidden, it can be better to create a separate part in the component just for the power pins.

Tips

1. Only one instance of this violation type will be listed in the Messages panel. When investigating the error using the Details region of the panel, a single entry will be listed reflecting the net which is being added. There may be multiple nets added - such as GND and VCC - but only one will be listed, determined by alphabetical order. If you clear the violation for a particular net, the next net (in order) will appear under this violation type.
2. It can be more efficient to edit pin properties in the SCHLIB List panel or the SCH List panel. Note that the Connect To pin property is called Hidden Net Name in the panel.