Working with the Flight Time - Rising Edge Design Rule on a PCB in Altium Designer

Created: 3月 17, 2022 | Updated: 3月 18, 2022 | Applies to version: 21

This document is no longer available beyond version 21. Information can now be found here: Flight Time - Rising Edge Rule for version 25

注記

利用できる機能は、Altium 製品のアクセスレベルによって異なります。Altium Designer ソフトウェアサブスクリプションの様々なレベルに含まれる機能と、Altium 365 プラットフォームで提供されるアプリケーションを通じて提供される機能を比較してください。

ソフトウェアの機能が見つからない場合は、Altium の営業担当者に連絡して詳細を確認してください。

Rule category: Signal Integrity

Rule classification: Unary

Summary Copy Link Copied

This rule specifies the maximum allowable flight time on signal rising edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes to drive the signal on the net to the threshold voltage (marking the transition from signal LOW to signal HIGH), less the time it would take to drive a reference load (connected directly to the output) to the threshold voltage.

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.

Constraints Copy Link Copied

Default constraints for the Flight Time - Rising Edge rule.

Maximum (seconds) - the value for the maximum permissible flight time on the rising edge of the signal.

How Duplicate Rule Contentions are Resolved Copy Link Copied

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application Copy Link Copied

Batch DRC and during Signal Integrity analysis.

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