Public Release Notes

New capability:

Added the ability to view voltages and current densities of vias.  Vias are now represented with appropriate color coding just as other power and ground shapes are.  Display of vias can be toggled as are layers.

New capability:

Added a ‘via wall thickness’ variable in the setup to comprehend vias as hollow objects.  The effective area of vias is derated appropriately to represent their increased resistance due to the missing material. See the Via Wall Thickness section of the documentation for more information.

Format change:

Improved the configuration file (*.pidc_confg) format by listing components with their full identifier, and not just by their reference designator. This is a significant change directed at making the Analyzer software more robust and capable, but will affect the portability of configuration files, since they will only be valid for the specific PCB from which they were generated.

Issues:

• Improved reporting of simulation failures by providing more information about the cause, rather than just cryptic error codes.
• Added preemptive disabling of simulations that will result in failures, when possible.
• Resolved simulation failure on ‘PWR580B’ design using virtual components.
• Resolved a Configuration loading issue where the changed ODB caused a virtual component mismatch.
• Fixed Analyzer use of ODB layer names instead of user layer names.
• Resolved customer design that fails for 0 thickness of ‘Plane2_1’, which doesn't exist.
• Fixed updating of Recent Designs list, which did not include a config that has been saved under a new name.
• Improved the separation of ‘Properties’ from ‘Criteria’ in the Source and Load selection dialog.
• Resolved erroneously high current density being reported at connection to source.
• Fixed layers not being shown for thick designs.
• Resolved simulation failure when devices touch multiple power rails.
• Fixed component selection, which prevented choosing the correct part if “j” has been typed after selecting the drop down.
• Fixed Results panel not showing voltage results at load.
• Resolved simulation failure when excitation has same pin designator for two pins.
• Fixed wording when simulation fails from “Simulation ran failed…” to “Simulation failed…”.
• Resolved simulation failure when multiple pins have been used on the source or load.
• Separated the “Properties” from the “Criteria” better in source and load selection dialogs.
• Fixed issue where the power path was made invalid when loading configurations.

In previous versions of PDN Analyzer, using the same designator for multiple pins would cause the simulation to fail with the following (or similar) error messages:

• [Error] <<error>>
• [Error] solver stopped due to exception:
• [Error] Traceback (most recent call last):
• [Error]   File "<string>", line 1, in <module>
• [Error]   File "altium_plugin\pidc.py", line 507, in create_plb_file
• [Error]   File "altium_plugin\pidc.py", line 494, in create_ICs
• [Error]   File "altium_plugin\pidc.py", line 455, in __init__
• [Error] KeyError: ('1',)
• [Error] <<end>>

This issue has now been resolved - simulations will complete successfully if the same pin designator is used for multiple pins.

In previous versions of PDN Analyzer, component names with spaces would cause the simulation to fail with the following (or similar) error messages:

• [Error]    Flex_6946.PcbDoc    PDN Analyzer    solver stopped due to exception:
• [Error]    Flex_6946.PcbDoc    PDN Analyzer    Traceback (most recent call last):
• [Error]    Flex_6946.PcbDoc    PDN Analyzer      File "<string>", line 1, in <module>
• [Error]    Flex_6946.PcbDoc    PDN Analyzer      File "altium_plugin\pidc.py", line 507, in create_plb_file
• [Error]    Flex_6946.PcbDoc    PDN Analyzer      File "altium_plugin\pidc.py", line 494, in create_ICs
• [Error]    Flex_6946.PcbDoc    PDN Analyzer      File "altium_plugin\pidc.py", line 360, in __init__
• [Error]    Flex_6946.PcbDoc    PDN Analyzer    AttributeError: 'NoneType' object has no attribute 'n_pins'

This issue has now been resolved - simulations will complete successfully if net names have spaces in them.

Check that load has non-zero amperage: entering 0A as a current sink is now not allowed.

Ensure valid stackup before enabling simulation. Checks stackup parameters and disables simulation if any are not valid:

• Invalid dielectric constant (<1).
• 0 thickness for dielectric or conductor.

Ensure a maximum of 2 nets in the path between the source and load power nets.  If there are more than 2 nets between the source and load power nets, the user will be prompted by; “Many nets between source and loads, proceed with simulation?” (Yes, No).  This warns the user that they may have built an erroneous path (see Source to Load path section in the PDN Analyzer Guide).

Report the cause of any red exclamation marks (!), so as to inform the user what has failed. If a red exclamation mark is shown, the failure will be printed in the messages dialog:

• "Error: Source <U#> exceeded max allowed PWR supply DC current magnitude. Allowed: x.xxxA, Actual: x.xxxA"
• "Error: Source <U#> exceeded max allowed PWR pin current magnitude. Allowed: x.xxxA, Actual: x.xxxA"
• "Error: Source <U#> exceeded max allowed GND pin current magnitude. Allowed: x.xxxA, Actual: x.xxxA"
• "Error: Load <U#> did not meet minimum required DC Voltage magnitude. Minimum: x.xxxV, Actual: x.xxxV"

The maximum current densities reported by the auto-scale did not agree with maximum current density found when probing.  For example, auto-scaling showed the maximum current density as 1.2GA/m², while probing indicated that the largest current density was 0.2GA/m² (the internal .json file verified a maximum current density of 1.2GA/m²).  The software issue has been resolved, and probing now agrees with that reported by the auto-scale.

PDN Analyzer was not interpreting strings correctly: when converting the string "0Rab", if a is zero, the zero is discarded.  This is now resolved.

Older pcbdoc's do not have a SimulationDummy.PcbDoc.htm file, so the simulation failed. This issue has been fixed.

Collection of data on errors. If you have agreed to participate in the Altium Product Improvement Program, the following data will be collected:

• If the simulation run was successful or not.
• Error codes and messages.
• Net count in the path, load count, source count, ODB file size, ODB++ generation time, and simulation run server time.