Signal Integrity - Slope - Rising Edge

Created: March 23, 2017 | Updated: September 26, 2019 | Applies to versions: 1.0, 1.1, 2.0, 2.1, 3.0, 3.1 and 3.2

Now reading version 2.1. For the latest, read: Signal Integrity - Slope - Rising Edge for version 4

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Rule category: Signal Integrity

Rule classification: Unary

Summary Copy Link Copied

This rule specifies the maximum allowable slope time on the rising edge of the signal. Rising edge slope is the time it takes for a signal to rise from the threshold voltage (VT), to a valid high (VIH).

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.

Constraints Copy Link Copied

Default constraints for the Slope - Rising Edge rule.

Maximum (seconds) - the value for the maximum permissible rising edge slope time.

How Duplicate Rule Contentions are Resolved Copy Link Copied

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application Copy Link Copied

Batch DRC and during Signal Integrity analysis.

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Content

Summary
Constraints
How Duplicate Rule Contentions are Resolved
Rule Application