Signal Integrity - Signal Top Value

Created: March 17, 2022 | Updated: March 18, 2022 | Applies to version: 4

This document is no longer available beyond version 4. Information can now be found here: Signal Top Value Rule for version 5

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Rule category: Signal Integrity

Rule classification: Unary

Summary Copy Link Copied

This rule specifies the minimum voltage level that a signal can settle to in the high state (the top value).

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.

Constraints Copy Link Copied

Default constraints for the Signal Top Value rule.

Minimum (Volts) - the value for the minimum permissible top value voltage.

How Duplicate Rule Contentions are Resolved Copy Link Copied

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application Copy Link Copied

Batch DRC and during Signal Integrity analysis.

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Content

Summary
Constraints
How Duplicate Rule Contentions are Resolved
Rule Application