Signals with no Load

Parent category: Violations Associated with Nets

Default report mode:

Summary

This violation occurs when a pin (with I/O Type Output or IO), or a sheet entry (with I/O Type Input or Bidirectional), is not connected to another part of the circuit (e.g. pin, port, sheet entry, power port, offsheet connector).

Notification

If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the Preferences dialog) an offending object will display a colored squiggle beneath it. A notification is also displayed in the Messages panel in the following format:

Signal <SignalName> has no load

where:

• SignalName is the name of the affected signal.

Recommendation for Resolution

If the offending pin or sheet entry is intended to be used within the design, ensure that it is connected to the relevant point in the circuit.

If the offending object is a component pin and you do not intend to use it within the design, simply place a No ERC directive on the pin.

If the offending object is a sheet entry that you do not intend to use, simply remove it from its parent sheet symbol.

Tips

1. This violation type will only be displayed when compiling an FPGA project (*.PrjFpg), a single source schematic that is part of an FPGA project, or a free schematic document.