Parent page: Tutorial - A Complete Design Walkthrough with Altium Designer
Main pages: PCB Design Rule Types , Defining, Scoping & Managing PCB Design Rules
Do I have the PCB Rules and Constraints Editor dialog?
Altium Designer suggests two distinct approaches to defining design constraints: the PCB Rule and Constraints Editor dialog and the Constraint Manager . The Constraint Manager is available in a PCB design project only if the Constraint Manager functionality was available at the moment of creating that project (provided you have the System.ConstraintManager option enabled in the Advanced Settings dialog ).
Note that this page applies only if the Constraint Manager is not available. To quickly check if the Constraint Manager is available for the tutorial project, open the Design main menu from the Schematic or PCB editor and check for the Constraint Manager command. If the Constraint Manager is available, skip this tutorial page and go to the next page: Component Placement and Routing the Board .
The PCB Editor is a rules-driven environment, meaning that as you perform actions that change the design, such as placing tracks, moving components, or autorouting the board, the software monitors each action and checks to see if the design still complies with the design rules. If it does not, then the error is immediately highlighted as a violation. Setting up the design rules before you start working on the board allows you to remain focused on the task of designing, confident in the knowledge that any design errors will immediately be flagged for your attention.
Design rules are configured in the
PCB Rules and Constraints Editor dialog , as shown below (
Design » Rules
). The rules are divided into ten categories, which can then be further divided into design rule types.
All PCB design requirements are configured as rules/constraints, in the PCB Rules and Constraints Editor .
Routing Width Design Rules
Design rule reference: Width
The width of the routing is controlled by the applicable routing width design rule, which the software automatically selects when you run the Interactive Routing command and click on a net.
When you are configuring the rules, the basic approach is to set the lowest priority rule to target the largest number of nets, and then add higher-priority rules to target nets with special width requirements, such as power nets. There is no issue if a net is targeted by multiple rules; the software always looks for and only applies the highest priority rule.
For example, the tutorial design includes a number of signal nets and two power nets. The default routing width rule can be configured at 0.25mm for the signal nets. This rule will target all nets in the design by setting the rule scope to All. Even though a scope of All also targets the Power nets, these can be specifically targeted by adding a second, higher-priority rule, with a scope of InNet('12V') or InNet('GND'). The image below shows the summary of these two rules, the detail is shown in the images in the following two collapsible sections.
Two Routing Width design rules have been defined, the lowest priority rule targets All nets, the higher priority rule targets objects in the 12V net or the GND net.
Routing Width and Routing Via Style design rules include Min, Max, and Preferred settings. Use these if you prefer to have some flexibility during routing, for example, when you need to neck a route down or use a smaller via in a tight area of the board. This can be done on the fly as you route by pressing 3 to cycle through the routing widths, or 4 to cycle through the via sizes. There are also other techniques for editing the routing width and via size as you route; these are discussed more in the routing section.
Avoid using the Min and Max settings to define a single rule to suit all sizes required in the entire design. Doing this means you forgo the ability to get the software to monitor that each design object is appropriately sized for its task.
Configuring the Routing Width Rule for the signal nets
With the PCB as the active document, open the PCB Rules and Constraints Editor .
Each rules category is displayed under the Design Rules folder (left-hand side) of the dialog. Double-click on the Routing category to expand the category and see the related routing rules then double-click on Width to display the currently defined width rules.
Click once on the existing Width rule to select it. When you click on the rule, the right-hand side of the dialog displays the settings for that rule including: the rule's Where The Object Matches in the top section (also referred to as the rule's scope – what you want this rule to target) with the rule's Constraints below that.
Since this rule is to target the majority of nets in the design (the signal nets), confirm that the Where The Object Matches setting is set to All. An additional rule will be added to target the power nets.
Edit the Width settings to be: Min Width = 0.2mm, Preferred Width = 0.25mm, Max Width = 0.25mm. Note that the settings are reflected in the individual layers shown at the bottom of the dialog. You can also configure the requirements on a per-layer basis.
The rule is now defined. Click Apply to save it and keep the dialog open.
The default Routing Width design rule has been configured.
Adding a Routing Width Rule for the power nets
The next step is to add another design rule to specify the routing width for the power nets. To add and configure this rule, open the PCB Rules and Constraints Editor dialog if not already.
With the existing Width rule selected in the Design Rules tree on the left of the dialog, right-click and select New Rule to add a new Width constraint rule, as shown in the animation below.
A new rule named Width_1 appears. Click on the new rule in the Design Rules tree to configure its properties.
Click in the Name field on the right and enter the name Width_Power in the field.
Click in the dropdown in the Where The Object Matches section and select Custom Query from the list. The dialog will change to include an edit box where the custom query is entered.
Click the Query Builder button to open the Query Builder dialog , then configure it to target objects: InNet('12V') or InNet('GND').
Click the Add first condition text, select Belongs to Net, then set the Condition Value to 12V.
Click the Add another condition text, select Belongs to Net, then set the Condition Value to GND.
The AND operator will have appeared between the two condition statements, click on it select OR from the dropdown.
Click the OK button to accept the query and return to the rules dialog.
Set the Constraints for the rule. Edit the Min Width / Preferred Width / Max Width values 0.25 / 0.5 / 0.5 to allow power net routing widths in the range 0.25mm to 0.5mm, as shown below.
This Width rule targets the power nets.
Click Apply to save the rules and keep the dialog open.
When there are multiple rules of the same type, the PCB editor uses the rule Priority to ensure the highest priority applicable rule is applied.
If you are adding rules:
When a new rule is added it is given the highest priority, and
When a rule is duplicated the copy is given priority below the source rule.
Click the Priorities button at the bottom of the dialog to change the priorities.
Defining the Electrical Clearance Constraint
Design rule reference: Clearance Constraint
The next step is to define how close electrical objects that belong to different nets can be to each other.
This requirement is handled by the Electrical Clearance Constraint. For the tutorial, a clearance of 0.25mm between all objects is suitable.
Note that entering a value into the Minimum Clearance field will automatically apply that value to all of the fields in the grid region at the bottom of the dialog. You only need to edit in the grid region when you need to define a clearance based on the object-type.
The electrical clearance constraint is defined between objects. Switch the Constraints to Advanced to display all object kinds.
Note that the Electrical Clearance Constraint has two object selection fields: Where The First Object Matches and Where The Second Object Matches . That is because this is a binary rule; it is a rule that applies between two objects.
Defining the Electrical Clearance Constraint
Expand the Electrical category in the tree of Design Rules then expand the Clearance rule-type.
Click to select the existing Clearance constraint. Note that this rule has two query fields; that is because it is a binary rule . The rules engine checks each object targeted by the setting Where The First Object Matches and checks it against the objects targeted by the Where The Second Object Matches setting to confirm that they satisfy the specified Constraints settings. For this design, this rule will be configured to define a single clearance between All objects.
In the Constraints region of the dialog, set the Minimum Clearance to 0.25mm, as shown in the image above.
Click Apply to save the rule and keep the dialog open.
Defining the Routing Via Style
Design rule reference: Routing Via Style
As you route and change layers, a via is automatically added. In this situation, the via properties are defined by the applicable Routing Via Style design rule. If you place a via from the Place menu, its values are defined by the in-built default primitive settings. For the tutorial, you will configure the Routing Via Style design rule.
A single routing via is suitable for all nets in this design.
Defining the Routing Via Style Design Rule
Expand the Routing category in the tree of Design Rules then expand the Routing Via Style rule-type and select the default RoutingVias design rule.
Since it is highly likely that the power nets can be routed on a single side of the board, it is not necessary to define a routing via style rule for signal nets and another routing via style rule for power nets. Edit the rule settings to the values suggested earlier in the tutorial, i.e. a Via Diameter = 1mm and a Via Hole Size = 0.6mm. Set all fields (Min, Max, Preferred) to the same size.
Click OK to save the changes and close the PCB Rules and Constraints Editor dialog.
Save the PCB file locally.
Existing Design Rule Violations
You might have noticed that the transistor pads are showing that there is a violation. Right-click over a violation and select the Violations in the right-click menu, as shown below. The details show that there is a:
Clearance Constraint violation
Between a Pad on the MultiLayer, and a Pad on the MultiLayer
Where the clearance is 0.22mm, which is less than the specified 0.25mm
Right-click on a violation to examine what rule is being violated and the violation conditions. In this image, the display is in single layer mode, with the Top Layer as the active layer.
This violation will be discussed and resolved shortly. If you find the violation markers distracting, you can clear them by running the Tools » Reset Error Markers command. This command only clears the marker; it does not hide or remove the actual error. The error will be flagged again the next time you perform an edit action that runs the online DRC (such as moving the component), or when you run the batch DRC.
Review the Design Rules
The default new board created by the software will include rules that are not needed in every design, and many other design rules will need to be adjusted to suit the requirements of your design. For this reason, it is very important to review the design rules. This can be done in the PCB Rules and Constraints Editor . Select Design Rules at the top of the tree on the left, then scan down the Attributes column for all of the rules and quickly locate any that need their values adjusted.
When you create a new board, it will include default design rules that might not be needed for your design. Redundant rules can be disabled by clicking on the Design Rules entry or a specific category entry in the PCB Rules and Constraints Editor and disabling the rules (clear the checkboxes in the Enabled column).
The default board also uses imperial units. If your board uses metric, there will be many rule values, such as the Soldermask expansion, that will change from rounded values like 4mil, to 0.102mm, or the Minimum Solder Mask Sliver default will change from 10mil to 0.254mm. While that least significant digit, for example, 0.002mm, is insignificant when it comes to output generation, you can edit these settings in the design rules if it bothers you.
Reviewing the design rules, note the column order can be changed if required.
Design rules can also be exported and stored in a .RUL file, then imported into future PCB designs. To do this, right-click in the tree on the left of the PCB Rules and Constraint Editor to open the Choose Design Rules dialog. Select the rules you want to export using the standard Windows selection techniques then click OK to export the selected rules.
