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Project Compiler Violations Reference

Created: September 22, 2017 | Updated: September 22, 2017 | Applies to versions: 18.0, 18.1, 19.0 and 19.1
Now reading version 18.0. For the latest, read: Project Compiler Violations Reference for version 21

The process of compiling is integral to producing a valid netlist for a project. In fact it is the process of compilation that yields the unified data model of a design - the single model of the data that is accessible across the design domains in Altium Designer's unified design environment. Connectivity awareness in your schematic diagram can be verified during compilation according to rules defined as part of the options for the design project - on the Error Reporting and Connection Matrix tabs respectively.

This area of the Altium Designer documentation provides a comprehensive reference describing each of the possible electrical and drafting violations that can exist in source documents when compiling a project.

For a detailed overview of verifying your captured design, see Compiling and Verifying the Design.

Violations are grouped into the following categories:

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Note

The features available depend on your Altium product access level. Compare features included in the various levels of Altium Designer Software Subscription and functionality delivered through applications provided by the Altium 365 platform.

If you don’t see a discussed feature in your software, contact Altium Sales to find out more.