Validating Your Design Project

Parent page: More about Schematics

What does it mean to compile the design? And why does the design need to be compiled; why can't the software just keep track of the connectivity as you create it on my schematic?

The software manages the connective data across the schematic and the PCB.

Ultimately, the software needs to build a connective model of the entire design for both the schematic and the PCB. To do this with persistence - where the software is keeping track of the connectivity at all times - the component and connective data for the entire design would need to be available when the design is opened, which would require all the data to be stored in a single file. Storing all of the data, for all of the sheets in your large multi-sheet schematic, in a single file is possible, but, for a number of reasons, is not the best approach.

To draw an analogy to software development, it would be like storing all of the source code for your entire application in a single file, and coding in a development environment that recompiles every time you you make a change. Neither of these are something that any coder would want. Software development tools allow the source to be spread across multiple files, and they separate the creation process from the analysis and compilation process. Doing this allows the developer to freely create, edit and modify their source code, using a file structure they choose. They compile the source to generate the working code only when they think it is ready for compilation. 

Using this same approach, the schematic designer can freely place, wire, re-arrange, re-name, and add and delete content from their schematic design. When the designer thinks it is ready, they compile it - verifying it and building the internal connective model. This approach also supports a one-file-per-schematic-sheet model. Using a separate file for each schematic means you can easily bring in content from a previous project, and it also means that multiple designers can work on the same project, at the same time.

When you are ready to compile the design, choose the Compile PCB Project command from the Project menu.

The software:

• Builds a netlist for each schematic sheet.
• Creates the sheet-to-sheet connectivity.
• Builds the Unified Data Model.
• Analyzes the complete design to check for drafting and electrical errors.

Using this approach, the schematic editor is actually an intelligent drafting tool, rather than a wiring tool. When you connect two pins with a wire you are drafting your design intentions, not creating an actual net. That net is not created until you compile the project, and that process is managed by code outside of the schematic editor. As mentioned, there are a number of advantages to this approach, with the biggest being that the compiled model of the design sits outside of the individual schematic and PCB editors. This compiled model is referred to as the Unified Data Model (UDM). The UDM includes detailed descriptions of every component in the design and how they connect to each other.

The Unified Data Model

A fundamental element of the software is the Unified Data Model (UDM). When the project is compiled, a single, cohesive model is created that sits central to the design process. Data within the model can then be accessed and manipulated by the various editors and services within the software. Rather than using a separate data store for each of the various design domains, the UDM is structured to accommodate all information from all aspects of the design, including the components and their connectivity.

The Unified Data Model makes all of the design data available to all of the editors, and helps deliver sophisticated design features, like multi-channel design and variants.

So how do you interact with the unified data model, for example, to trace a net through the design? You do that through the Navigator panel.

Examining the Connectivity in the Navigator Panel

Reference article: Navigator panel

If the design is large and spread over many sheets, it can become difficult to follow a net and verify the connectivity in the design by simply looking at the schematics. To help with this process, the Navigator panel is used. The panel gives a view of the entire, compiled design so it will be blank until the project is compiled (Project » Compile PCB Project). The Navigator panel can be opened by clicking the Panels button on the bottom right of the design window then selecting Navigator.

To use the panel:

• Set the browsing behavior by clicking the  button at the top of the panel to open the System - Navigation page of the Preferences dialog to enable your preferred Highlight Methods. Alternatively, right-click on the object of interest in the panel then use the context menu options to configure the navigation behavior.
• Set the scope of your browsing in the first section of the panel. To browse the entire design select Flattened Hierarchy.
• Click on a component in the Instance section of the list to jump to that component, to expand the component to locate, and to jump to a pin.
• Click on a net or bus in the Net / Bus section to jump to that net or bus, to expand the component to locate, and to jump to a pin.

Click on a component or net in the Navigator panel to locate that component or net and trace the connectivity through the design. Right-click to access display options.

Verifying the Components

Main article: More about Components and Libraries

A key aspect of verifying the design is to be confident that the components are correct. Typically this is done as the components are added to your company libraries. Common component errors that will cause board design errors include:

• Invalid footprint reference - the component references a footprint that is not available. During transfer of the design from the schematic editor to the PCB editor, the software looks in the Components panel for the footprint according to the PCB Library option selected for each footprint in the PCB Model dialog.
• Pins do not match pads - the component symbol pin numbers do not match the footprint pad numbers. The software assumes a one-to-one match, for example, schematic symbol pin 4 matches PCB pad number 4. This is not mandatory. If they do not match, the pin-to-pad mapping must be defined as part of the component creation process in the PCB Model dialog.

Other component errors that cause design delays and frustrations include:

• Incorrect default designator.
• Incorrect schematic pin specifications, such as the Electrical Type.
• Missing design detail, such as the component specs, the part number, the data sheet reference, etc.
• Incorrectly defined hidden power pins. In a multi-part component, these should be assigned to Part zero to ensure they are present regardless of which part(s) of the component have been placed on the schematic.

Configuring the Verification Options

Main article: Project Options dialog

There are a large number of drafting and electrical checks that can be performed on the compiled design. These are configured as part of the project options. Click Project » Project Options to open the Project Options dialog (shortcut: C, O). The default settings will not suit every design and, therefore, it is important to become familiar with the options and how to configure them to suit your design.

Drafting Checks

When you compile, common drafting and editing errors are checked in accordance with the settings in the Error Reporting tab of the Project Options dialog.

Configure the required error checks.

The error checks are organized in groups, for example Violations Associated with Nets, Violations Associated with Components, etc. The groups are listed alphabetically in the dialog.

The Report Mode of each violation can be changed to one of four values by clicking on it and selecting the desired value in the drop-down: Fatal Error, Error, Warning, No Report.

Generally it is better to first compile the design and examine the warnings with the default settings. For those warnings that are not an issue for the current design, the reporting level can be changed.

Connectivity Checks

The electrical connectivity is checked in accordance with the settings in the Connection Matrix tab of the Project Options dialog.

The Connection Matrix defines which each electrical conditions are allowed and which are not allowed.

The matrix provides a mechanism to establish connectivity rules between component pins and net identifiers, such as Ports and Sheet Entries. It defines the logical or electrical conditions that are to be reported as warnings or errors. For example, an output pin connected to another output pin would normally be regarded as an error condition, but two connected passive pins would not.

Click on the small square in the matrix to change a particular rule.  Each rule determines the reporting level for a given pin/net identifier combination. There are four possible values for each rule: Fatal Error, Error, Warning, and No Report.

Interpreting Messages and Locating Errors

Main article: Messages panel

When the project is compiled, every condition that generate a warning or error is listed in the Messages panel. Note that the Messages panel will only open automatically if there is an error condition. To check for warnings, you will need to open it. Click the Panels button on the bottom right of the application to display the Messages panel. Once the project has been compiled, the panel will list any warnings and errors that have been detected.

The Messages panel displays the detected warnings and errors detected in the project.

The Messages panel is command central for presenting compiler violations. Things to be aware of include:

• Nets with no driving source (Violations associated with Nets section) - if the net does not include a pin with the Electrical Type of Output or I/O, this error will occur. There are many valid situations that can cause this, for example, a net from a connector pin to an input pin.
• Nets with multiple names (Violations associated with Nets section) - if you change the name of a net (for example, you connect a named net to a sheet entry with a different name (which is permitted) because that sheet entry name better reflects the net's function on the lower-level child sheet), this error will occur. It also occurs in a multi-channel design where the software must assign a unique name to each repeated net.
• Component Revision has Inapplicable State (Violations associated with Components section) - this check results in the message Can't perform revision state validation. It occurs when there is a component that has been placed from a server and that server does not support revision state validation.
• The Messages panel has two regions - the upper grid region summarizes the warnings/errors; the lower region gives details of the currently selected warning/error.
• Double-click on a message to cross-probe to that warning/error. Double-click on a detail to show that specific object.
• You can click on any of the Messages panel column headings (e.g., Class, Document, Message) to assist in sorting the errors and warnings.
• Right-click in the Messages  panel to Clear messages or to Export them to a report.
• The panel includes warnings and errors detected from settings in both the Error Reporting tab and the Connection Matrix tab.
• An interactive Place Specific No ERC dialog opens by clicking  in the Wiring toolbar. The dialog presents a list of current compile warnings/errors, supports cross probing to an error and placing a pre-configured specific No ERC directive on the chosen error. 
• When you right-click on a warning/error in the Messages panel then select the Place Specific No ERC for this violation command, you will automatically cross probe to the error location and a No ERC directive will appear on the cursor, ready to place on the error location. Press Tab to edit the properties of the directive prior to placement, if required:
  • As a generic directive, suppress all error checks at the point that the directive is placed.
  • As a specific directive, only suppress the specified error checks at the point that the directive is placed.

Resolving a Warning or Error

It is important to address each warning or error that is detected. The default error settings tend to be conservative since it is better for the software to err on the side of being cautious and let you decide if the testing boundaries can be relaxed. For example, your design may require IO pins to be connected to Input ports, requiring you to adjust the appropriate cell in the Connection Matrix tab. Another common error check to be changed is the Net has no driving source, requiring you to disable that check in the Error Reporting tab.

There will be situations when you want to test the entire design for a certain condition, but you want to ignore a warning/error at a specific point in the circuit. For example, you might want to allow a net to be renamed at a specific location, but only in that location. This can be done by placing a No ERC directive at that location.

Using the No ERC Directive

Main article: No ERC object

When you need to allow a specific point in the circuit to not report an error, place a No ERC (Electrical Rules Check) directive on that point (Place » Directives » Generic No ERC) meaning "do not flag a warning/error at this location". Set the No ERC symbol style and color to suit its role in the circuit in the No ERC mode of the Properties panel.

Place No ERC directives to suppress warnings or errors at a specific location.

Note that No ERC directives can be excluded from printouts, if required, by enabling the relevant option(s) in the Schematic Print Properties dialog.

You can place a Specific No ERC directive directly at the error location from the Messages panel (right-click then choose Place Specific No ERC for this violation as shown in the images below) or at the violation .

The right-click command makes it easy to place a specific No ERC directive directly at the error location, either from the Messages panel or at the violation.

More about Compiler Errors

The software can test for a large number of potential error conditions. There is information available about each error check in the Project Compiler Violations Reference.