Working with the Slope - Falling Edge Design Rule on a PCB in Altium NEXUS

Created: März 17, 2022 | Updated: März 18, 2022 | Applies to version: 4

This document is no longer available beyond version 4. Information can now be found here: Slope - Falling Edge Rule for version 5

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Rule category: Signal Integrity

Rule classification: Unary

Summary

This rule specifies the maximum allowable slope time on the falling edge of the signal. Falling edge slope is the time it takes for a signal to fall from the threshold voltage (VT), to a valid low (VIL). Constraints.

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.

Constraints

Default constraints for the Slope - Falling Edge rule.

Maximum (seconds) - the value for the maximum permissible falling edge slope time.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application

Batch DRC and during Signal Integrity analysis.

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