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Working with the Slope - Rising Edge Design Rule on a PCB in Altium NEXUS

Created: 三月 17, 2022 | Updated: 三月 18, 2022 | Applies to version: 4

This document is no longer available beyond version 4. Information can now be found here: Slope - Rising Edge Rule for version 5

This documentation page references Altium NEXUS/NEXUS Client (part of the deployed NEXUS solution), which has been discontinued. All your PCB design, data management and collaboration needs can now be delivered by Altium Designer and a connected Altium 365 Workspace. Check out the FAQs page for more information.

 

Rule category: Signal Integrity

Rule classification: Unary

Summary

This rule specifies the maximum allowable slope time on the rising edge of the signal. Rising edge slope is the time it takes for a signal to rise from the threshold voltage (VT), to a valid high (VIH).

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.

Constraints

Default constraints for the Slope - Rising Edge rule.Default constraints for the Slope - Rising Edge rule.

  • Maximum (seconds) - the value for the maximum permissible rising edge slope time.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application

Batch DRC and during Signal Integrity analysis.

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