Violations Associated with Buses when Validating a Design in Altium Designer

Default report mode:

Summary

This violation occurs when the index of a constituent net connected to a bus lies outside the range specified by the net to which the bus is associated.

Notification

If validation errors and warnings are enabled for display on the schematic (enabled on the Schematic – Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:

Bus index out of range on <NetPrefix> Index = <NetIndex>

where:

• NetPrefix is the prefix of the constituent net connected to the bus (e.g., A for net A8, connected to a bus associated to net A[0..7]).
• NetIndex is the erroneous index of the constituent net (e.g., net A8 has an index of 8).

Recommendation for Resolution

With the violation selected in the Messages panel, use the Details region of the panel to quickly cross probe to the net label associated with the offending net and either amend the index of the net so that it lies within the correct range, or rename the net altogether. The latter would be typical if you have named the net by mistake and it is not a constituent of the net transported by the bus object.

Notes

• Use the controls associated with the Object Hints entry in the Connectivity Insight Options region (the System – Design Insight page of the Preferences dialog) to determine the launch style for object hints (Mouse Hover and/or Alt+Double Click).
• When you need to allow a specific point in the circuit not to report a violation of this type, you can place a Specific No ERC directive directly at the error location from the Messages panel – you can do this by right-clicking a message reporting the violation to suppress, then choosing the Place Specific No ERC for this violation command.

Default report mode:

Summary

This violation occurs when the syntax of the net to which the bus is associated is specified incorrectly.

Notification

If validation errors and warnings are enabled for display on the schematic (enabled on the Schematic – Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:

Bus range syntax error <NetName> at <Location>

where:

• NetName is the name of the parent net to which the offending bus object is associated.
• Location is the X, Y coordinates for the offending bus object's electrical hotspot.

Recommendation for Resolution

With the violation selected in the Messages panel, use the Details region of the panel to quickly cross probe to the offending net identifier (e.g., net label, port, sheet entry, etc) whose bus syntax is defined incorrectly. The correct syntax should appear in one of the following formats:

• NetName[LowerIndex..UpperIndex]
• NetName[UpperIndex..LowerIndex]

For example, consider a bus that carries two constituent nets, A0 and A1. The bus syntax in this case should be A[0..1] or A[1..0]. Examples of incorrect syntax would include: A[0.1], A[1-0], A[0,1], A[..1], and A[0..].

Notes

• Use the controls associated with the Object Hints entry in the Connectivity Insight Options region (the System – Design Insight page of the Preferences dialog) to determine the launch style for object hints (Mouse Hover and/or Alt+Double Click).
• When you need to allow a specific point in the circuit not to report a violation of this type, you can place a Specific No ERC directive directly at the error location from the Messages panel – you can do this by right-clicking a message reporting the violation to suppress, then choosing the Place Specific No ERC for this violation command.

Default report mode:

Summary

This violation occurs when at least one index in the syntax for a net associated with a bus is negative in value.

Notification

If validation errors and warnings are enabled for display on the schematic (enabled on the Schematic – Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:

Illegal bus range value <BusLabel> at <Location>

where:

• BusLabel is the defined bus labeling where the illegal value has been detected.
• Location is the X, Y coordinates for the offending bus object's electrical hotspot.

Recommendation for Resolution

With the violation selected in the Messages panel, use the Details region of the panel to quickly cross probe to the offending net object (e.g., net label, port, sheet entry, etc.,) whose bus syntax is defined incorrectly. The correct syntax should appear in one of the following formats:

• <NetName>[<LowerIndex>..<UpperIndex>]
• <NetName>[<UpperIndex>..<LowerIndex>]

Notes

• Use the controls associated with the Object Hints entry in the Connectivity Insight Options region (the System – Design Insight page of the Preferences dialog) to determine the launch style for object hints (Mouse Hover and/or Alt+Double Click).
• When you need to allow a specific point in the circuit not to report a violation of this type, you can place a Specific No ERC directive directly at the error location from the Messages panel – you can do this by right-clicking a message reporting the violation to suppress, then choosing the Place Specific No ERC for this violation command.

Default report mode:

Summary

This violation occurs when two net identifiers associated with the same bus slice define bus labels with ordering that is not in the same direction (ascending or descending).

Notification

If validation errors and warnings are enabled for display on the schematic (enabled on the Schematic – Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:

Mismatched bus ordering on <NetName> Low value first and High value first

where:

• NetName is the name of the parent net to which the mismatched bus ordering is associated.

Recommendation for Resolution

With the violation selected in the Messages panel, use the Details region of the panel to quickly trace the affected bus slice and identify the net identifiers (port, net label, sheet entry, etc.,) whose bus ordering is not consistent. Determine the correct ordering and amend the naming for the erroneous object.

Notes

• Use the controls associated with the Object Hints entry in the Connectivity Insight Options region (the System – Design Insight page of the Preferences dialog) to determine the launch style for object hints (Mouse Hover and/or Alt+Double Click).
• When you need to allow a specific point in the circuit not to report a violation of this type, you can place a Specific No ERC directive directly at the error location from the Messages panel – you can do this by right-clicking a message reporting the violation to suppress, then choosing the Place Specific No ERC for this violation command.

Default report mode:

Summary

This violation occurs when two net identifiers associated with the same bus slice define bus labels with differing widths. For example, a port, with the name A[0..7], might be connected to a bus whose attached net label is defined as A[0..15].

Notification

If validation errors and warnings are enabled for display on the schematic (enabled on the Schematic – Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:

Mismatched bus widths on bus section <NetName> (<BusSize1> and <BusSize2>)

where:

• NetName is the name of the parent net to which the mismatched bus objects are associated.
• BusSize1 is the width of the first of the offending bus objects.
• BusSize2 is the width of the second of the offending bus objects.

Recommendation for Resolution

With the violation selected in the Messages panel, use the Details region of the panel to quickly trace the affected bus slice and identify the net identifiers (port, net label, sheet entry, etc.), the bus label widths of which are not consistent. Determine the correct width and amend the naming for the erroneous object.

Notes

• Use the controls associated with the Object Hints entry in the Connectivity Insight Options region (the System – Design Insight page of the Preferences dialog) to determine the launch style for object hints (Mouse Hover and/or Alt+Double Click).
• When you need to allow a specific point in the circuit not to report a violation of this type, you can place a Specific No ERC directive directly at the error location from the Messages panel – you can do this by right-clicking a message reporting the violation to suppress, then choosing the Place Specific No ERC for this violation command.

Default report mode:

Summary

This violation occurs when a wire object is incorrectly connected to a bus, or a bus object is incorrectly connected to a wire. For example, port A might be connected to a bus, but the correct bus label syntax (e.g., A[0..1]) has not been entered for the port's name. In effect, the port is a single signal (or wire) object that is now erroneously connected to a bus.

Notification

If validation errors and warnings are enabled for display on the schematic (enabled on the Schematic – Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:

<ObjectIdentifier> at <Location> placed on a <ObjectType>

where:

• ObjectIdentifier represents the mismatched object, which can be either a bus or wire object (e.g., pin, port, power port, net label, off-sheet connector, sheet entry). The identifier will appear in one of the following two formats:
  • For a bus – Bus <Object> <Name> (e.g. Bus Net Label GND_BUS[..]).
  • For a wire – Wire <Object> <Name> (e.g. Wire Port TXD).
• Location is the X,Y coordinates for the object's electrical hotspot.
• ObjectType is the object on which the offending object has been placed – either a wire or a bus.

Recommendation for Resolution

With the violation selected in the Messages panel, use the Details region of the panel to quickly cross probe to the offending object. To resolve the issue, consider the following:

• Is the connection correct? – should a bus connecting to the object really be a wire and vice versa?
• Is the object defined correctly? – for a bus object, ensure that the object's name is specified using the correct bus syntax in the form <Name>[<LowIndex>..<HighIndex>] or <Name>[<HighIndex>..<LowIndex>]. For example, a byte-wide data output port might be specified as DAT_OUT[7..0]. For a wire object, ensure that the object's name defines a single signal and is not defined using bus syntax.

Note

Use the controls associated with the Object Hints entry in the Connectivity Insight Options region (the System – Design Insight page of the Preferences dialog) to determine the launch style for object hints (Mouse Hover and/or Alt+Double Click).

Default report mode:

Summary

This violation occurs when two net identifiers (port, net label, sheet entry, etc.,) connected to the same bus slice differ in their bus syntax – one defines a bus range in numeric format (e.g., A[0..2]), while the other defines the range in a generic format (e.g., A[0..b]).

Notification

If validation errors and warnings are enabled for display on the schematic (enabled on the Schematic – Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:

Mismatched generic and numeric bus labeling on <NetName> <Level> value first and Generic

where:

• NetName is the name of the parent net to which the mismatched bus labeling is associated.
• Level depends on the numeric ordering for the net. If ascending (e.g., [0..2]) Level will appear as Low. If descending (e.g., [2..0]) Level will appear as High.

Recommendation for Resolution

With the violation selected in the Messages panel, use the Details region of the panel to cross-probe to the offending objects. Determine which of the objects is erroneous in its bus label specification and change it accordingly.

Notes

• Use the controls associated with the Object Hints entry in the Connectivity Insight Options region (the System – Design Insight page of the Preferences dialog) to determine the launch style for object hints (Mouse Hover and/or Alt+Double Click).
• When you need to allow a specific point in the circuit not to report a violation of this type, you can place a Specific No ERC directive directly at the error location from the Messages panel – you can do this by right-clicking a message reporting the violation to suppress, then choosing the Place Specific No ERC for this violation command.