Справочник по нарушениям компиляции проекта

When you connect two pins with a wire, you are drafting your design intentions, not creating an actual net. The net is not created until the project is compiled. As well as extracting details about the components and how they are connected, compiling also extracts detailed component and design parametric information. The compiled model of the project is referred to as the Unified Data Model.

In versions of the software prior to Altium Designer 20.0, the project had to be manually compiled to build the Unified Data Model. Since then, the design data model is incrementally updated after each user operation through dynamic compilation - creating what is referred to as the Dynamic Data Model (DDM). There is no manual compilation of the project involved, it is all done automatically.

The process of validating is integral to producing a valid netlist for a project. Connectivity awareness in your schematic diagram can be verified during compilation according to rules defined as part of the options for the design project - on the Error Reporting and Connection Matrix tabs respectively.

This area of the Altium Designer documentation provides a comprehensive reference describing each of the possible electrical and drafting violations that can exist in source documents when validating a project.

Violations are grouped into the following categories:

• Violations Associated with Buses
• Violations Associated with Components
• Violations Associated with Connections - Multi-board Design Projects only
• Violations Associated with Documents
• Violations Associated with Harnesses
• Violations Associated with Mated Parts - Multi-board Design Projects only
• Violations Associated with Nets
• Violations Associated with Others
• Violations Associated with Parameters