Working with the Fabrication and Assembly Testpoint Style Design Rule on a PCB in Altium Designer

Rule category: Testpoint

Rule classification: Unary

Summary

The Fabrication Testpoint Style and Assembly Testpoint Style design rules specify the allowable physical parameters of pads and vias that are to be considered for use as testpoints for bare-board fabrication testing, or in-circuit assembly testing respectively. The constraints between these two rules are identical. 

Constraints

Default constraints for the Fabrication and Assembly Testpoint Style rule.

Sizes

The following options allow you to specify pad/via diameter and hole size criteria when testing for valid testpoints:

• Min Size – specifies the minimum permissible diameter for a pad/via to be considered as a testpoint.
• Max Size – specifies the maximum permissible diameter for a pad/via to be considered as a testpoint.
• Preferred Size – specifies the diameter to be used for testpoint pads/vias placed by the Autorouter.
• Min Hole Size – specifies the minimum permissible hole size for a pad/via to be considered as a testpoint.
• Max Hole Size – specifies the maximum permissible hole size for a pad/via to be considered as a testpoint.
• Preferred Hole Size – specifies the hole size to be used for testpoint pads/vias placed by the Autorouter.

Clearances

The following options allow you to define clearance constraints specific to board testing:

• Min Inter-Testpoint Spacing – specifies the minimum permissable center-to-center distance to be observed between two adjacent testpoints, when considering a pad/via for use as a testpoint. This is typically determined by the probe head spacing for the flying probe, or bed-of-nails test fixtures, being used in the testing.
• Component Body Clearance – specifies the minimum permissable distance to be observed between a testpoint and the body of a component, when considering a pad/via for use as a testpoint. If a component has a component body, then the clearance is applied to the component body. If a component body is absent, then the clearance is applied to the component's non-pad/via primitive objects on the Mechanical + TopOverlay/BottomOverlay layers.
• Board Edge Clearance – specifies the minimum permissable distance to be observed between a testpoint and the edge of the board, when considering a pad/via for use as a testpoint.
• Distance to Pad Hole Centers - specifies the minimum permissable distance from the center of a testpoint, to the center of an adjacent pad (the center of the pad's hole).
• Distance to Via Hole Centers - specifies the minimum permissable distance from the center of a testpoint, to the center of an adjacent via (the center of the via's hole).

Grid

Use of a grid is most appropriate when targeting a non-custom bed-of-nails fixture. To include use of a grid, enable the Use Grid option. To disable use of a grid, enable the No Grid option.

If you do want to use a grid, the following options allow you to define it in a more comprehensive manner:

• Origin – the X and Y coordinates, specified relative to the current board origin. This allows you to align the grid with the origin of a bed-of-nails fixture.
• Grid Size – specifies the size of the grid to be used when attempting to find valid testpoint sites (pads and/or vias). If the entry is changed to zero, the No Grid option will automatically be selected upon applying the change.
• Tolerance – specifies the maximum permissable tolerance to use when considering how far from a specified grid a pad or via can be located and still be considered a valid testpoint location.

Allowed Side

Use these options to specify on which side of the board prospective testpoint pad/via locations can reside – either Top, Bottom, or both.

Allow Testpoint Under Component

Use this option to enable the use of pads/vias located underneath components (on the same side of the board as the components) for testpoint purposes. This option would typically be enabled in a Fabrication Testpoint Style rule, but not for an Assembly Testpoint Style rule – as the pad/via will typically not be accessible once the board is populated with components.

Rule Scope Helper

Use this region of the constraints to determine which objects the rule is to apply to. Simply enable the checkbox for the objects to be included – SMD Pads, Vias, Thru-hole Pads – and click on the Set Scope button. The logical query for the rule scope will be created and entered into the Full Query region for the rule.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application

This rule is obeyed by the Testpoint Manager, the Autorouter, the Online and Batch DRC and during output generation. The Online DRC and Batch DRC test all attributes of the rule except the Preferred Size and Preferred Hole Size – these settings are used by the Autorouter to define the size of testpoint pads/vias that the Autorouter places.

Tips

1. If you want to use a surface mount pad as a testpoint, the minimum hole size should be set to zero.
2. When specifying use of a grid, if a pad/via assigned as a testpoint is not on the grid specified by the Grid Size option, it will cause a violation when performing a Design Rule Check (DRC). For example, if you set the Grid Size to 25mil, then the testpoints must be on a 25mil grid. If the testpoints do not lie on any particular grid, you can either enter a value for Grid Size that will accommodate all testpoints (the minimum setting is 0.001 mil), or you can simply specify the No Grid option.