PCB_Cmd-TestpointManagerTestpointManager_AD

Applied Parameters: None

Summary

This command is used to manage the testpoints on your board, from the centralized Testpoint Manager dialog. The Testpoint Manager allows you to assign testpoints - for bare-board fabrication testing and/or in-circuit assembly testing - in a far more streamlined and automated fashion, based on defined design rules. This automated assignment simply sets the relevant testpoint properties for the pad/via in each case. You of course have the option to manually specify testpoints – in essence, handcrafting at the individual pad/via level – giving you full control over the testpoint scheme employed for your board.

Access

This command is accessed from the PCB Editor by choosing the Tools » Testpoint Manager command, from the main menus.

Use

After launching the command, the Testpoint Manager dialog will appear. Use the dialog to automatically assign and clear testpoints from the one convenient location. A listing of all nets in the design is provided, with status to indicate testpoint coverage – either Complete or Incomplete – for both bare-board fabrication and in-circuit assembly testing.

Click the Fabrication Testpoints or Assembly Testpoints buttons to access commands for assigning or clearing that type of testpoint. Note that you can manually select nets in the upper region of the dialog to selectively assign/clear testpoints.

The Status Summaries region provides a full summary of the testpoint status for the board, for both testing modes. This region updates with each assignment or clearance action performed. For more lower-level detail, use the Assignment Results region. This will give detail, for example, on the number of top/bottom pads/vias involved in an assignment/clearance.

Tips

1. The Testpoint Manager adheres to defined Fabrication and Assembly Testpoint Style and Fabrication and Assembly Testpoint Usage rules. These rules are identical, in terms of constraints, between the two testing modes (fabrication and assembly). The style rule essentially specifies constraints that a pad or via has to meet in order to be considered for selection as a testpoint location. The usage rule simply specifies which nets require a testpoint.
2. For a more conceptual overview regarding testpoints, including pointers to consider when defining a strategy to incorporate testpoints into a design, see Adding Testpoints to the Board.