TRANSLATE: KB: 레이어 스택에서 계산된 전송 임피던스 검증
Created: May 07, 2024 | Updated: November 15, 2024
Altium Designer
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[왜] 레이어 스택에서 계산된 전송 임피던스를 검증해야 하는가? 결과가 다른 제3자 계산기/도구와 일치하지 않기 때문입니다.
[무엇] 본질적인 차이점은, 닫힌 형태의 수식에 기반한 웹 계산기와 Altium의 Layer Stack Manager 내에서 수행되는 Simbeor의 2D 준정적 필드 솔버에 기반한 숫자 계산 사이에 있습니다. 이는 Method of Moment에 기반하며 수렴, 비교, 측정에 의해 검증됩니다.
[어떻게] Layer Stack Manager에서 'Use Surface Finish' 및 'Use Solder Mask'와 같은 세부 옵션을 확인하세요. 이는 웹 계산기 결과와의 차이를 설명할 수 있습니다. 또한, 참조 평면도 자주 간과되는 또 다른 파라미터입니다. 결론적으로, 보드 제조업체와 상의하고 추후에 수정할 여지를 남기기 위해 트레이스 폭/간격을 과대 평가하여 유지하세요.
Solution Details Copy Link Copied
You can read more here:https://www.altium.com/documentation/altium-designer/interactively-routing-controlled-impedance-pcb#!the-simbeor-sfs
https://forum.live.altium.com/#/posts/249000/783549
Additionally, options such as 'Use Surface Finish' and 'Use Solder Mask' in Layer Stack Manager could attribute to the difference from a web calculator result, typically without such consideration.
Reference plane is also another parameter frequently overlooked, and if unspecified for Coplanar configuration, Altium assumes that it is on the same layer as the signal with S (clearance) being the only dependent parameter associated with adjacent conductors.
https://www.altium.com/documentation/altium-designer/interactively-routing-controlled-impedance-pcb#!support-for-coplanar-transmission-line-structures
If you also have no reference on each side of the routing then theoretically this is not coplanar i.e. "impedance controlled" it is just differential pair routing. Ultimately you could consider adjusting the spacing "S" to the ground shielding to a significantly large value. If you are making these type of adjustments you should consider any possible ramifications from those settings.
Here is another paper comparing web calculators and Simbeor SFS integrated in Layer Stack Manager since its inception in 2020:
https://resources.altium.com/sites/default/files/2020-03/Impedance%20Calculation_fin2.pdf
The bottom line, however, is that it is best that you consult your board fabricator upfront, and when in doubt, try to stay with an oversized estimation for trace width/gap, so that you have a room in your board later to narrow them after you solidify the spec with your fabricator. Here is another forum thread on the topic discussed among other expert users:
https://forum.live.altium.com/#/posts/251714/798646
It is also worth mentioning that there is a convenient command Retrace to update existing trace width/gap of an obsolete impedance profile in one go.