Working with the Slope - Rising Edge Design Rule on a PCB in Altium Designer

Rule category: Signal Integrity

Rule classification: Unary

Summary

This rule specifies the maximum allowable slope time on the rising edge of the signal. Rising edge slope is the time it takes for a signal to rise from the threshold voltage (VT), to a valid high (VIH).

Constraints

Default constraints for the Slope - Rising Edge rule.

• Maximum (seconds) - the value for the maximum permissible rising edge slope time.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application

Batch DRC and during Signal Integrity analysis.