Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. In RF designs stitching is used in combination with guard rings to create a via wall, helping create an electromagnetically 'quiet' PCB. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net to that net.
Via shielding has a different function, in RF designs it is used to help reduce crosstalk and electromagnetic interference in a route that is carrying an RF signal. A via shield, also known as a via fence or a picket fence, is created by placing one or more rows of vias alongside the signal's route path. In Altium Designer, this is referred to as via shielding.
Altium Designer supports both via stitching and via shielding. In the image below, shielding vias are highlighted, move the cursor over the image to highlight the stitching vias that have been added to this board.
Use the Via Stitching and Via Shielding commands to stitch copper on different layers, and to add a wall of shielding vias adjacent to a route path (hover to highlight stitching vias).
Let's look at stitching vias first, and then shielding vias.
Via stitching is run as a post-process, filling free areas of copper with stitching vias. For via stitching to be possible, there must be overlapping regions of copper that are attached to the specified net, on different layers. Supported regions of copper include Fills, Polygons and Power Planes.
Select the Tools » Via Stitching/Shielding » Add Stitching to Net command from the menus to add stitching vias to a specific net. The Add Stitching to Net dialog will open, where the Stitching Parameters and Via Style are specified.
Options and Controls of the Add Stitching to Net Dialog
Stitching Parameters
The stitching parameters control the stitching vias' placement pattern and their clearance from other-net and same-net objects.
Constrain Area - enable to constrain via stitching to a specific area. After selecting the option, you will be taken to the design space. After using the cross-hair cursor to define the constrain area, right-click to return to the dialog.
Edit Area - click to edit the constrain area.
Offset - enter the X and Y offset distance(s).
Grid - the distance between the center of adjacent stitching vias. Stitching vias will not be placed in violation of applicable design rules; if a potential via site would result in a violation that site is skipped.
Stagger alternate rows - alternate rows of shielding vias are offset by half of the Grid value.
Same Net Clearances
There are two ways of controlling the clearance of stitching vias to vias and pads on the same net: either the applicable Clearance design rule is used or the Default Via/Pad Clearance specified here is used. If a rule exists, the tighter of these settings is used. These options behave as follows:
Create new clearance rule - a stitching via-versus-other via/pad design rule is created when this button is clicked. This rule setting is used to ensure a potential stitching site is valid. When clicked, the PCB Rules and Constraints Editor dialog opens in which the rule Constraints can be set. Note that the rule is named and scoped to target the net selected in the dialog.
Edit Clearance Rule - if an applicable design rule already exists, this button will be present instead of the Create New Clearance Rule button. Click to change the Constraint rule settings.
Default Via/Pad Clearance - stitching vias are only placed on potential stitching sites if this much clearance exists. Since potential stitching sites are determined by the stitching grid, it is likely they will be further than apart than this setting.
Min Boundary Clearance - stitching vias are only placed on potential stitching sites if this much clearance exists to the edge of Polygon/Fill/Plane regions.
The clearance from a stitching via to objects on other nets is controlled by the applicable clearance design rule. A stitching via will not be placed on a potential stitching site if it will violate the applicable design rule.
Via Style
The stitching Via Style can be configured manually or imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. Clicking this button will load the Preferred rule settings.
Diameters
Simple - Via Style(Hole size and diameter) is the same through all layers.
Hole size - specify the hole size value for the Via.
Tolerance Mi n/Max - setting hole tolerance attributes can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
Diameter - specify the diameter for the Via.
Top-Middle-Bottom - different Hole Size and Diameters can be set at Top Layer, Middle Layer and Bottom Layer respectively.
Hole size - specify the hole size value for the Via.
Tolerance Mi n/Max - setting hole tolerance attributes can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
Top Layer - specify via size for top layer.
Middle Layer - specify via size for Middle layer.
Bottom Layer - specify via size for Bottom layer.
Full Stack - different Hole Size and Diameters can be edited at each layer(including all signal layers and planes).
Hole size - specify the hole size value for the Via.
Tolerance Mi n/Max - setting hole tolerance attributes can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
Edit Full Stack Via Sizes - click to open the Via Layer Editor dialog in which you can specify via settings for each layer including shape, size, and X/Y location.
The Via Layer Editor dialog
Attributes on Layer
Diameter - the diameter of the via.
Layer Stack Reference
Name - the layer referenced by the via layer. This field is not editable.
Index - the relative index of the layer.
Absolute Layer
Name - name of the layer, which is defined by default. This field is not editable.
Index - absolute index of the via among all layers (including hidden layers). This field is not editable.
Only show layers in layerstack - enable this option to display only the layers (derived from the Layer Stack Manager ) in the Layer Stack. Check the Layer Stack Manager (Design » Layer Stack Manager ) to see which layers are used. If this option is disabled, all the available PCB layers are displayed.
Via Template
Template - select a via template from the dropdown.
Library - displays to which library the via template is linked and includes the option to Unlink the template from said library.
Properties
Drill Pair - the layers on which this via starts and ends.
Net - the net to which the via is currently assigned. Change the net assignment by clicking in the field and choosing a net from the drop down list. Select No Net to specify that the via is not connected to any net. The Net property of a primitive is used by the Design Rule Checker to determine if a PCB object is legally placed.
Locked - enable this option to protect the via from being edited graphically. Lock a via whose position is critical. If you try to edit a primitive that is locked, you will be informed that the primitive is locked and asked if you want to proceed with the action. If this option is unchecked, the primitive can be freely edited without confirmation.
The Start Layer and End Layer settings define a via to be one of the following types:
Multi-layer (Thru-Hole ) - this type of via passes from the Top layer to the Bottom layer and allows connections to all internal signal layers.
Blind - this type of via connects from the surface of the board to an internal electrical layer.
Buried - this type of via connects from one internal electrical layer to another internal electrical layer.
Solder Mask Expansions
Expansion value from rules - enable this option to allow the existing solder mask expansion rule to take effect on this pad object. Check the Mask design category from the PCB Rules and Constraints Editor dialog.
Specify expansion value - enable this option to edit the expansion value and the solder mask expansion design rule is overridden for this pad.
Force complete tenting on top - enable to override any solder mask settings in the solder mask expansion design rules which results in no opening in the solder mask on top layer of this pad.
Force complete tenting on bottom - enable to override any solder mask settings in the solder mask expansion design rules which results in no opening in the solder mask on the bottom layer of this pad. Disable this option and this pad is affected by a solder mask expansion rule or specific expansion value.
Additional Controls
Via Types - click to open the Layer Stack Manager in which you can configure the via types for the active layer stack.
Tips
Once stitching is complete, you will need to re-pour the polygons if the applicable Polygon Connect Style design rule specifies a relief connection style.
Tools » Via Stitching » Remove Via Stitching Group command, then clicking on any via in the group.
Using the selected net, the stitching algorithm identifies all Fills, Polygons and Power Planes attached to that net and attempts to connect them through the board, using the specified via and stitching pattern.
The via stitching algorithm treats Polygons, Fills and Planes in the following way:
Polygons and Fills that are on the same net are stitched wherever they overlap on different layers. If there are Polygons or Fills on other nets that are overlapping within that area (on another layer), stitching is not applied in that region. Overlapping Plane regions on other nets are passed through.
Overlapping Plane regions on the target net are always stitched, regardless of the presence of Plane regions (on another layer) attached to other nets. Rule 1 above applies if there are Polygons or Fills overlapping in the same region.
To summarize these two rules - on other layers, other-net Plane layers are always punched through by stitching vias, but other-net Polygons or Fills are not. If the design includes other-net Polygons within an area that requires stitching vias, temporarily shelve those polygon(s), define the stitching vias, then un-shelve and re-pour the polygon(s). Learn more about shelving and re-pouring polygons .
Configuring the Stitching Parameters
Notes about the Add Stitching to Net dialog settings:
Select the Net to be used for stitching first as this effects the behavior of other options, such as clicking the Load values from Routing Via Style Rule button. The Net dropdown is toward the bottom of the dialog, in the middle.
The Grid is the distance between the centers of adjacent stitching vias and applies in the X and Y directions. Stitching vias will not be placed in violation of applicable design rules if a potential via site would result in a violation, that site is skipped.
If the Stagger alternate rows option is enabled, alternate rows of stitching vias are offset by half of the Grid value.
The Same Net Clearance options control the clearance between stitching vias and vias and pads on the same net. There are two ways of controlling the clearance between same-net objects, either the applicable Clearance design rule is used, or the Default Via/Pad Clearance specified in the dialog is used. If an applicable rule exists, then the tighter of these two settings is used. Use the Create new clearance rule button to add a new Clearance design rule into the rules dialog, based on the settings you have entered in the Default Via/Pad Clearance field.
The stitching Via Style can be configured manually, or it can be selected from those available in the Template dropdown, or it can be imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. Clicking this button will load the Preferred rule settings.
Each set of stitching vias are added to a union, set the PCB panel to Unions mode to locate and examine the vias included in a via stitching set.
A stitching set can be removed by running the Tools » Via Stitching » Remove Via Stitching Group command, then clicking on any via in that set.
Constraining the Via Stitching to an Area
As well as covering the entire board, stitching vias can be constrained to a user-defined area. When the stitching is within a user-defined area, that area of vias can be interactively moved and resized, if required.
Enable the Constrain Area option to restrict stitching vias to a user-defined area.
To constrain via stitching to a specific area, enable the Constrain Area checkbox in the Add Stitching to Net dialog, as shown above. As soon as you enable this option the dialog will close and the cursor will change to a crosshair, ready to define the area - note the Status bar, it will prompt Select the first point of the area .
The process of defining a via stitching area is the same as defining a solid region or a polygon, you:
click to define a series of vertices (corners),
right-click to drop out of placement mode and automatically close and complete the area.
During placement there are a number of different corner modes available:
Press Shift+Spacebar to cycle through the corner modes (you might find the right-angle corner mode the most appropriate),
Press Spacebar to toggle the corner direction,
Press the 1 shortcut to toggle between placing 1 or 2 edges with each click.
Press Shift+Spacebar to cycle corner modes, Spacebar to toggle the corner direction, 1 to toggle between placing 1 edge or 2 with each click.
Once the area is defined you will return to the Add Stitching to Net dialog, so you can configure the rest of the settings. Click OK when this is complete, Altium Designer will then analyze the area, identify potential via sites, and place the stitching vias.
Modifying a User-Defined Via Stitching Area
The set of vias in each unique area of via stitching are clustered into a Union (a set of objects that the PCB editor recognizes as a single group). The entire union can be moved, and the area can also be resized.
To modify via stitching that is constrained to an area:
Drag a select-within rectangle (left-to-right) so that it includes one or more of the stitching vias. The boundary of the stitching area will be displayed, as shown in the animation below.
To move a stitching union - position the cursor within the area, when the move cursor
To resize the stitching union by moving an edge - position the cursor over the edge, when the move edge cursor
To resize the stitching union by moving a vertex - position the cursor over the edge, when the move vertex cursor
After you release the mouse button you will be prompted to Re-generate via stitching? , click Yes to update the via stitching in the new location /shape.
Drag a selection window to select a stitching area, then move or resize by positioning the mouse to get the correct cursor.
To place a via shield around a routed net, select the Tools » Via Stitching/Shielding » Add Shielding to Net command from the menus. The Add Shielding to Net dialog will appear with which to configure the Shielding Parameters and Via Style as required. The vias will be placed along both sides of the chosen net, wherever it is possible to place a via that complies with the applicable design rules.
Options and Controls of the Add Shielding to Net Dialog
The shielding parameters control the shielding vias' placement pattern and their clearance from other-net and same-net objects.
Net to shield - net to have shielding vias placed around.
Selected Objects - place shielding vias around the selected objects, rather than the net selected in the Net to shield field. Can also be used to shield multiple selected nets .
Stagger alternate rows - alternate rows of shielding vias are offset by half of the Grid value.
Row Spacing - spacing between rows of shielding vias (edge to edge separation) when the Rows setting is greater than 1.
Distance - separation from the edge of the shielded net track segments, to the edge of the shielding vias.
Grid - the distance between the edges of adjacent shielding vias. Shielding vias will not be placed in violation of applicable design rules; if a potential via site would result in a violation, then that site is skipped.
Rows - number of rows of shielding vias.
Add shielding copper - place a polygon over the area occupied by the shielding vias, connected to the net specified in the Via Net field. The polygon is defined in accordance with the applicable Clearance constraint and Polygon Connect Style design rules.
Add clearance cutout - include a polygon cutout around the shielded net, set back from the net by the distance specified in the Distance field. Use this when you require a different clearance from the applicable Clearance constraint design rule.
Via Style
The shielding Via Style can be configured manually by selecting the desired style or can be imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. Clicking this button will load the Preferred rule settings.
Diameters
Simple - Via Style (Hole size and diameter) is the same through all layers.
Hole size - specify the hole size value for the Via.
Tolerance Mi n/Max - setting hole tolerance attributes can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
Diameter - specify the diameter for the Via.
Top-Middle-Bottom - different Hole Size and Diameters can be set at Top Layer, Middle Layer and Bottom Layer.
Hole size - specify the hole size value for the Via.
Tolerance Mi n/Max - setting hole tolerance attributes can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
Top Layer - specify via size for top layer.
Middle Layer - specify via size for Middle layer.
Bottom Layer - specify via size for Bottom layer.
Full Stack - different Hole Size and Diameters can be edited at each layer (including all signal layers and planes).
Hole size - specify the hole size value for the Via.
Tolerance Mi n/Max - setting hole tolerance attributes can help determine the fits and limits of your board. Specify the Minimum (-) and Maximum (+) hole tolerance for the design.
Edit Full Stack Via Sizes - click to open the Via Layer Editor dialog in which you can specify via settings for each layer stack.
Via Template
Template - select a via template from the drop-down.
Library - displays which library the via template is linked to and includes the option to Unlink the template from said library.
Properties
Drill Pair - the layers on which this via starts and ends.
Net - the net to which the via is currently assigned. Change the net assignment by clicking in the field and choosing a net from the drop down list. Select No Net to specify that the via is not connected to any net. The Net property of a primitive is used by the Design Rule Checker to determine if a PCB object is legally placed.
Locked - enable this option to protect the via from being edited graphically. Lock a via whose position is critical. If you try to edit a primitive that is locked, you will be informed that the primitive is locked and asked if you wish to proceed with the action. If this option is unchecked, the primitive can be freely edited without confirmation.
The Start Layer and End Layer settings define a via to be one of the following types:
Multi-layer (Thru-Hole ) - this type of via passes from the Top layer to the Bottom layer and allows connections to all internal signal layers.
Blind - this type of via connects from the surface of the board to an internal electrical layer.
Buried - this type of via connects from one internal electrical layer to another internal electrical layer.
Solder Mask Expansions
Expansion value from rules - enable to allow the existing solder mask expansion rule to take effect on this pad object. Check the Mask design category from the PCB Rules and Constraints Editor dialog.
Specify expansion value - enable to edit the expansion value and the solder mask expansion design rule is overridden for this pad.
Force complete tenting on top - enable to override any solder mask settings in the solder mask expansion design rules and results in no opening in the solder mask on top layer of this pad. Disable this option and this pad is affected by a solder mask expansion rule or specific expansion value.
Force complete tenting on bottom - enable to override any solder mask settings in the solder mask expansion design rules and results in no opening in the solder mask on the bottom layer of this pad.
Additional Controls
Via Types - click to open the Layer Stack Manager in which you can configure the via types for the active layer stack.
Tips
Tools » Via Stitching/Shielding » Remove Via Shielding Group command, then clicking on any via in the group.
Configuring the Shielding Via Parameters
Notes about the Add Shielding to Net dialog and using shielding vias:
Select the Net to be shielded first, as this affects the behavior of other options, such as clicking the Load values from Routing Via Style Rule button.
Partial net shielding or multiple-net Shielding, using the Selected Objects option:
If you do not want to shield the entire net, select the required track segments first, run the Add Shielding to Net command, then enable the Selected Objects option.
To shield multiple adjacent nets, select the nets and shield with the Selected Objects option enabled.
Note that a differential pair can be shielded using the multiple-net Selected Objects technique, or by choosing either one of the differential pair nets in the Net to Shield dropdown.
Use the Add shielding copper option to add a polygon that encloses the shielding vias, include the Add clearance cutout option to clip the polygon back to just enclose the vias. Read the Including Shielding Copper with the Stitching topic below to learn more about these options.
The shielding Via Style can be configured manually, or it can be selected from those available in the Template dropdown, or it can be imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. Clicking this button will load the Preferred rule settings.
The size and positioning of the shielding vias is not an exact science, but there are guidelines that have been established based on empirical testing.
As noted in the discussion forum (5) , for a PCB with an onboard antenna, "the distance between vias should be 1/4 your resonant wavelength at the most."
The forum discussion also references a technical note(6) , which states that "the common rule of thumb is to locate stitch vias no further apart than λ λ
M K Armstrong, in his paper titled PCB design techniques for lowest-cost EMC compliance Part 1 (7) recommends:
"stitching at no more than λ /20, with stub lengths no longer than this. This is actually a very good rule for stitching any ground fill to the ground plane on a multi-layer design. λ is the wavelength of the highest significant frequency for the design (assume a frequency of 1 GHz if not know) where:
f = C / λ
NB: C (speed of light) will be approx. 60% of free-space velocity for EM radiation propagating through an FR4 dielectric PCB."
Including Shielding Copper with the Stitching
As well as adding shielding vias along each side of the routing, you can also include shielding copper, as shown in the image below. To do this, enable the Add shielding copper option. This copper is created as a polygon, so it obeys the applicable Clearance and Polygon Connect Style design rules.
The Add shielding copper option will add a polygon that encloses the shielding vias. The polygon edge that is away from the shielded net will touch the edge of the vias. The polygon edge that is adjacent to the shielded net will be set back from the net by the applicable Clearance design rule. If the Add clearance cutout option is also enabled, the polygon will instead be set back from the shielded net by the Distance setting in the Add Shielding to Net dialog. Hover the cursor over the image below to see the difference.
Shielding vias around a net with the clearance cutout option enabled, move the cursor over the image to disable the clearance cutout option.
The style of the connection from the shielding vias to the shielding copper (polygon) can be controlled by including a Polygon Connect Style design rule, targeted at the shielding vias and polygon. Use the InViaShielding query keyword to scope this design rule, so that it specifically targets those vias and that polgyon.
Identifying Vias that are Part of a Stitching or Shielding Array
Each via in a stitching or shielding array is identified by the addition of a string to the net name, such as [VS1], as shown in the image below, where:
VS - V ia S titching, and the numerical value identifies this via as belonging to the same via stitching union as other vias with the same identifier.
VSH - V ia SH ielding, and the numerical value identifies this via as belonging to the same via shielding union as other vias with the same identifier.
Vias that belong to an array have an additional string, such as [VS1] for [Via Shielding group 1], and [VSH4] for [Via SHielding group 4], appended to their net name.
Selecting or Editing Stitching or Shielding Vias
To simplify the process of working with an array of stitching/shielding vias, both kinds are automatically clustered into a union.
Selecting using the PCB Panel
To select the array, switch the PCB panel to Unions mode and select the required Via Stitching or Via Shielding union. All vias that are part of that array will select if the Select checkbox is enabled in the panel (as shown in the image below). Alternatively, double click on any via in the array to open the Properties panel and edit the array.
Use the PCB panel in Unions mode to select all vias in a stitching or shielding array. In this image, all four via shielding unions are selected.
Selecting Interactively
Selection behavior:
An individual stitching/shielding via can be selected and deleted.
If the Popup Selection Dialog option is enabled (PCB Editor - General page of the Preferences dialog), clicking on an individual via that belongs to a union will display a list that includes the union, as shown in the image above. When a union is selected, that union of vias can be deleted in the workspace.
If the Popup Selection dialog is not enabled, then clicking on an individual via that belongs to a union will behave in the following way:
The first click will select the individual via.
The second and subsequent clicks will select the next object in the selection order used when there are overlapping objects: for example component, polygon, via union (if those objects are under the cursor).
Alternatively, after the first click selects the individual via, press the Shift+Tab shortcut to invoke the Select Overlapping command. Continue pressing Shift+Tab to cycle through the overlapping objects, selecting each in turn.
A stitching union that is constrained to an area can be selected by dragging a select-within window around any via in the union (drag left-to-right), as demonstrated in the animation in the Modifying a User-Defined Via Stitching Area section of this page.
Editing Stitching or Shielding Vias
The properties of a stitching or shielding via set can be edited once it has been selected, in the Via Stitching or the Via Shielding mode of the Properties panel. Double-click on any via in the set to open the panel.
An example of an edit being performed to a via shielding.
As soon as any property has been edited in the panel, the Changes pending message and buttons appear at the top of the panel - click the Apply link to complete your editing action.
Shielding Parameters
Net – the net being shielded by the shielding vias.
Stagger alternate rows – alternate rows of shielding vias are offset by half of the Grid value when this option is enabled.
Row Spacing – spacing between rows of shielding vias (edge to edge separation) when the Rows setting is greater than 1.
Distance – separation from the edge of the shielded net track segments, to the edge of the shielding vias.
Grid – the distance between the edges of adjacent shielding vias. Shielding vias will not be placed in violation of applicable design rules; if a potential via site would result in a violation then that site is skipped.
Rows – number of rows of shielding vias.
Add Shielding – place a polygon over the area occupied by the shielding vias, connected to the net specified in the Via Net field. The polygon is defined in accordance with the applicable Clearance constraint and Polygon Connect Style design rules.
Add Clearance Cutout – include a polygon cutout around the shielded net, set back from the net by the distance specified in the Distance field. Use this when you require a different clearance from the applicable Clearance constraint design rule.
Via Template
Template – displays the currently chosen via template. Use the drop-down to change the assigned via template.
Library – displays to which library the via template is linked and includes the option to Unlink the template from said library.
Properties
Net – the net that the shielding vias are connected to.
Via Type – use the drop-down to select the type of via from those available in the layer stack.
Via Types – click to open the Layer Stack to configure the required via types for the active layer stack.
Hole Information
Hole Size – size of the hole in the shielding vias.
Tolerance – negative and positive hole size tolerances allowed for the shielding vias.
Size and Shape
Size and Shape – vias are one of three styles:
Simple – the via diameter is the same on all layers
Top-Middle-Bottom – the via diameter can be specified for the Top layer, Middle (all internal layers), and Bottom layer.
Full Stack – the via diameter can be specified for every signal layer.
Diameter – diameter of the shielding vias.
Thermal Relief – check the Direct box then click Connect Style dialog to specify the connection style.
Solder Mask Expansion
Rule – enable this option to allow the existing solder mask expansion rule to take effect on the shielding vias. Check the Mask design category from the PCB Rules and Constraints Editor dialog .
Manual – enable this option to edit the mask expansion values (below) for these shielding vias.
Top – enter the required mask expansion for the Top Layer.
Bottom – enter the required mask expansion for the Bottom Layer.
Top Tented – if this checkbox is enabled, the mask is closed on the Top Layer for these shielding vias.
Bottom Tented – if this checkbox is enabled, the mask is closed on the Bottom Layer for these shielding vias.
Linked – if the Linked option is enabled, the same expansion value is used for both the Top and Bottom layers.
From Hole Edge – enable this option to calculate the mask expansion from the edge of the drill hole instead of the edge of the via donut.
Stitching Parameters
Constrain Area – enable to constrain via stitching to a specific area. After selecting the option, you will be taken to the design space. After using the cross-hair cursor to define the constrain area, right-click to return to the dialog.
Edit Area – click to edit the constrain area.
Offset (X/Y) – enter the X and Y offset distance(s). The stitching pattern will be placed within the constrain area, starting at an offset of the specified X and Y amount.
Grid – the distance between the center of adjacent stitching vias. Stitching vias will not be placed in violation of applicable design rules; if a potential via site would result in a violation that site is skipped.
Stagger alternate rows – alternate rows of shielding vias are offset by half of the Grid value.
Default Via/Pad – stitching vias are only placed on potential stitching sites if this much clearance exists. Since potential stitching sites are determined by the stitching grid, it is likely they will be further apart than this setting.
Min Boundary – stitching vias are only placed on potential stitching sites if this much clearance exists to the edge of Polygon/Fill/Plane regions.
Via Template
Template – displays the currently chosen via template. Use the drop-down to change the assigned via template.
Library – displays to which library the via template is linked and includes the option to Unlink the template from said library.
Properties
Via Type – use the drop-down to select the type of via from those available in the layer stack.
Via Types – click to open the Layer Stack to configure the required via types for the active layer stack.
Hole Information
Hole Size – size of the hole in the stitching vias.
Tolerance – negative and positive tolerances allowed for the stitching vias.
Size and Shape
Size and Shape – vias are one of three styles:
Simple – the via diameter is the same on all layers
Top-Middle-Bottom – the via diameter can be specified for the Top layer, Middle (all internal layers), and Bottom layer.
Full Stack – the via diameter can be specified for every signal layer.
Diameter – diameter of the stitching vias.
Thermal Relief – check the Direct box then click Connect Style dialog to specify the connection style.
Solder Mask Expansion
Rule – enable this option to allow the existing solder mask expansion rule to take effect on the stitching vias. Check the Mask design category from the PCB Rules and Constraints Editor dialog .
Manual – enable this option to edit the mask expansion values (below) for these stitching vias.
Top – enter the required mask expansion for the Top Layer.
Bottom – enter the required mask expansion for the Bottom Layer.
Top Tented – if this checkbox is enabled, the mask is closed on the Top Layer for these stitching vias.
Bottom Tented – if this checkbox is enabled, the mask is closed on the Bottom Layer for these stitching vias.
Linked – if the Linked option is enabled, the same expansion value is used for both the Top and Bottom layers.
From Hole Edge – enable this option to calculate the expansion from the edge of the drill hole instead of the edge of the via donut.
Updating the Polygons After Editing a Stitching/Shielding Union
Once stitching is complete, you will need to re-pour the polygons if the applicable Polygon Connect Style design rule specifies a relief connection style. This can be done using the commands in the Tools » Polygon Pours sub-menu.
Further Reading
For information about all aspects of PCB design, refer to the Printed Circuit Design and Fab Magazine website. The site is an excellent resource for technical topics, such as the role of a "via fence" (include the quote marks to improve the quality of the search results).
Wikipedia article, Via Fence
Studies on Via Coupling on Multilayer Printed Circuit Boards
A paper that introduces the basic principals of EM wave propagation within a PCB structure - Best practice in circuit board design
A discussion forum where the question Via fences for noise reduction of a chip antenna?
PCB design and layout techniques for lowest-cost EMC compliance, and signal integrity : M K Armstrong. EMC Standards, August 1999.
