Pin Package Delay
In every high-speed design over 500 MHz, the connection medium, or bond wire to the die, introduces a delay to the signal. This in-device delay is referred to as the pin-package delay. Even if two devices are fully pin-compatible from a design and PCB standpoint, package flight times will be different across different devices, so they will need to be accounted for. Flight time information can be found within the IBIS 6 document for the device. The Package Pins information should be considered during the I/O planning stage, or after synthesis for an FPGA. All device manufacturers should be able to supply the package delays, which will be specified either as a picosecond delay or as a length.
The delay can be included in your design either as a Pin Package Length or as a Propagation Delay, using the respective fields for the pin in the schematic editor or the pad/via in the PCB editor. The values entered are handled as follows:
Pin Package Length - all pin package lengths within each net are added in the PCB editor to give the Total Pin/Package Length, which is included in the overall Signal Length for that net. Refer to the Nets mode of the PCB panel to learn more about the Signal Length.
Propagation Delay - all user-defined delay values defined for pins/pads and vias in each net are added to the routing delay for that net in the PCB editor. The routing delay is automatically calculated by the Simbeor® field solver built into the Layer Stack Manager. Pad and via delays are not calculated automatically but can be user-defined.
Including the Delay in the Schematic
Pin package lengths can be defined as an attribute of the schematic component pin in the Properties panel in Pin mode. The software will default to use the Units of the underlying document, enter the units with the value, if required.
Enter the pin-package length with the required units.
- Component pin properties can also be edited in the library editor or on the schematic sheet on the Pins tab of the Properties panel in Component mode. Click
in that tab of the panel to open the Component Pin Editor, where all properties for all of the pins in that component can be edited. Values can be edited directly in the grid (select a cell and type in a new value), and the cursor keys can be used to move to the adjacent cells. Default units will automatically be added if they are not typed in. - Alternatively, use the SCHLIB List panel to copy/paste multiple Pin/Pkg Lengths or Propagation Delay values from a datasheet into a set of selected component pins in the schematic library editor – show image.
- As well as pasting clipboard content directly into selected cells, you can also right-click in the panel to access the Smart Grid Paste dialog, giving greater control over the process of bringing additional data into the pins – learn more about Editing Attributes with the Smart Grid Tools.
Defining the Delay in the PCB Editor
The Pin Package Length and Propagation Delay values are transferred to PCB layout as seen in the Pad mode of the Properties panel.
The Pin Package Length and Propagation Delay values are transferred from the schematic to the PCB, or they can also be defined directly in the PCB.
Examining the Pin/Package Length and the Propagation Delay in the PCB Panel
The Pin/Pkg Length is automatically included in the Signal Length calculations, which are displayed in various modes of the PCB panel. Set the panel to Nets mode to examine (or edit) the value of the Pin/Pkg Length for the pins in the chosen net. Note how the Routed Length column reflects the length of the routing, and the Signal Length column reflects the length of the routing plus any Pin/Pkg Lengths in that net.
The Pin/Pkg Length and its impact on the Signal Length is shown in the Nets mode of the PCB panel.
In the image below the propagation Delay column shows that there are two pairs of xSignals that are failing a Matched Length design rule. Because the highlighting is in the Delay column, it indicates that the rule is configured to use Delay Units rather than Length Units.
The Delay column shows that there are two pairs of xSignals that are failing a Matched Length design rule.
How the Length is Included in xSignals
The Pin/Pkg Length is automatically included in the overall xSignal length when:
- That signal is part of an xSignal definition
- That pad is not connected in a fly-by routing pattern (there is only one trace connected to that pad)