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Ver: Version: 19.1
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Signal Integrity - Slope - Rising Edge

Created: March 23, 2017 | Updated: September 26, 2019 | Applies to versions: 18.0, 18.1, 19.0, 19.1, 20.0, 20.1 and 20.2
Now reading version 19.1. For the latest, read: Signal Integrity - Slope - Rising Edge for version 21
 

Rule category: Signal Integrity

Rule classification: Unary

Summary

This rule specifies the maximum allowable slope time on the rising edge of the signal. Rising edge slope is the time it takes for a signal to rise from the threshold voltage (VT), to a valid high (VIH).

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.

Constraints

Default constraints for the Slope - Rising Edge rule.Default constraints for the Slope - Rising Edge rule.

  • Maximum (seconds) - the value for the maximum permissible rising edge slope time.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application

Batch DRC and during Signal Integrity analysis.

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Note

The features available depend on your Altium product access level. Compare features included in the various levels of Altium Designer Software Subscription and functionality delivered through applications provided by the Altium 365 platform.

If you don’t see a discussed feature in your software, contact Altium Sales to find out more.

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