Defining the Via Types for Use with Your Board

The Role of the Via

Vias are used to create the vertical, or layer-to-layer connections in a printed circuit board.

In the early days of board fabrication, all of the vias passed all the way through the board, from one side to the other. These thru-hole vias are drilled after the layers are fabricated and the routing etched. The conductive via barrels are formed in the drilled holes using an electroless plating process, completing the layer-to-layer connections.

The development of PCB fabrication technology saw the introduction of multilayer boards, and with it, the ability to drill vias between other pairs of layers. By drilling vias at certain points during the fabrication process, it was possible to create vias that only spanned two adjacent signal layers. These are referred to as blind vias (from a surface layer to the next layer in) and buried vias (between two internal layers).

Improvements in fabrication techniques and the introduction of laser drilling gave the ability to create very small (<10 mil) vias, formed from a surface layer to the next signal layer down. These are referred to as µVias. By creating µVias as the layers are built-up during the fabrication process (referred to as sequential lamination, or sequential build-up), it is now possible to form a stack of µVias that deliver seamless layer-to-layer signal transitions.

All of these Via Types are supported in Altium Designer.

All of the various types of vias that can be fabricated can be defined in the Via Types tab of the Layer Stack Manager.

Defining a Via Type

1. To define a new Via Type, switch to the Via Types tab of the Layer Stack Manager. Here you define the Z-plane layer-spanning requirements of each of the via types that are needed for your design. When you open the Via Types tab it will include a single, thru-hole via type.  For a two-layer board the default via is named Thru 1:2, the naming reflecting the via type, and the First and Last layers that the via spans. The default thru-hole span cannot be deleted.
2. The properties of the currently selected Via Type are edited in the Layer Stack Manager mode of the Properties panel. If the panel is not visible, click the  button at the bottom right of the application to enable it.
3. Click the  button to add an additional Via Type, then select the layers that this Via Type spans in the Properties panel. The new definition will have a name of <Type> <FirstLayer>:<LastLayer> (eg, Thru 1:2). The software will automatically detect the type (e.g. Thru, Blind, Buried) based on the layers chosen, and name the Via Type accordingly.
4. Configure the First Layer and Last Layer settings to define the span of this Via Type.
5. If a µVia is required, enable the µVia checkbox. This option will be only available when the via spans adjacent layers, or adjacent +1 (referred to as a Skip via).
6. If the Stack Symmetry option is enabled in the Board region of the Properties panel, the Mirror option will become available. When Mirror is enabled a mirror of the current via, spanning the symmetrical layers in the layer stack, is automatically created - enable this if required. 
7. Save the Stackup to make the changes available in the PCB editor.

Defining the Via Properties

The Via Types tab of the Layer Stack Manager is used to define the layer-spanning (Z-plane) requirements of each via type. The size properties of the via, including the diameter and hole size, are not defined in the Via Types tab.

The size properties of the via are defined by:

• manually editing a placed via in the Properties panel, or
• the PCB default primitives, when a via is placed manually (Place » Via), or
• the Routing Via Style design rule, if the via is placed during interactive routing or autorouting.

Configuring the Routing Via Style Design Rule

Main article: Constraining the Design - Design Rules

Vias that are placed during interactive routing or ActiveRouting have their size properties controlled by the applicable Routing Via Style design rule. To help target vias in the design rule, there is a set of via-related query keywords that you can use in the rule scope (Where the Object Matches), these are detailed below.

When you perform a layer change as you route, the software looks at the start and stop layers for this layer change, and chooses an allowed Via Type from the Layer Stack Manager. It then identifies the highest priority applicable Routing Via Style design rule and applies the via size settings from the Constraints section of that rule, to the via about to be placed.

For example, you might have a set of DRAM_DATA nets that require µVias for the TopLayer - to - S2 layer transition and the S2 - to - S3 layer transition and a drilled thru-hole via for all other layer transitions (which is also different to the via required by other nets). This can be handled by creating two Routing Via Style design rules to target these DRAM_DATA nets. An example of a suitable µVia design rule is shown below, hover the cursor over the image to show the thru-hole design rule.

Design rules can be scoped to apply to specific types of vias.

Query Keywords

To simplify the process of scoping Routing Via Style design rules, the following via-related query keywords are available:

Placing a Via as you Route

When you change layers during interactive routing the software will automatically insert a via. As described above, the via that is chosen depends on:

• The available Via Type(s) for the layers being spanned in the layer change.
• The applicable Routing Via Style design rule for the Via Type selected for that layer change.

Stacked µVias being placed during a layer change from L1 to L4. The Interactive Routing mode of the Properties panel displays the Via Type (s) that will be placed, press 6 to cycle through the possible via stacks,
press 8 to display a list of possible via stacks.

Controlling the Via Placed during Interactive Routing

• As you change routing layers the software automatically chooses the most suitable Via Type to suit that layer span.
• If there are multiple Via Types/combinations (via stacks) that can be used - press the 6 shortcut key to interactively cycle through all via stacks available for that layer change, press the 8 shortcut to display a list. Via stacks are presented in the order: use µVia(s), use Skip µVia, use Blind via, use Thruhole via. Stacked vias can be placed if the layer change is more than one layer, and suitable Via Types are defined. The proposed Via Type(s) are detailed on the Status bar and in the Heads Up display, for example [µVia 1:2, µVia 2:3, µVia 3:4], as shown in the image above.
• The last-used via stack is retained as the default for the next net you route. The default via stack is retained for the current editing session only.
• The via size properties are specified by the applicable Routing Via Style design rule, strategies for defining a suitable Routing Via Style design rule are discussed above.
• To interactively change the via's size as a layer-change is being performed, press the 4 shortcut. This will cycle through the Via Size modes: Rule Minimum; Rule Preferred; Rule Maximum; User Choice; with the current Via-Size mode being displayed on the Heads Up display and the Status bar (as shown in the image above). If User Choice is selected, press Shift+V to open the Choose Via Sizes dialog, and select a preferred via size. The list of available via sizes displayed in the dialog is taken from the list of vias already used in the design, inspect these in the Pad and Via Templates mode of the PCB panel.
• A side view of the proposed Via Type(s) is shown in the Properties panel, as shown above.
• To place a via and continue routing on the same layer, press the 2 shortcut.
• To place a via and suspend routing of this connection, press the / shortcut on the numeric keypad.
• Press Shift+F1 as you route for a menu of all in-command shortcuts.

Working with Placed Vias

• The layer numbers in the via span can be displayed inside all via types, toggle the Via Span display on and off in the View Options tab of the View Configuration panel.
• If there are stacked vias, the displayed numbers are the start and end layers of all vias in the stack. Hover the cursor over the image below to show the vias in 3D, on the right of the image is a stack of three vias.
• Working with stacked vias:
  • Stacked vias that form a continuous connection can be worked with as if they are a single via, click and drag on the stack to move them all, with the attached routing.
  • Click once to select the uppermost Via in the stack. If the mouse is not moved, subsequent single-clicks will select each of the other Vias in the stack, in turn.
  • Ctrl+Click and drag to move only the selected Via with its attached routing.
  • To select all Vias in a stack, click once to select one, then press Tab to extend that selection to include all Vias in that stack.

The spanned layers can be displayed in the vias. Hover the cursor to show the vias in 3D.

µVias (MicroVias)

µVias are used as the interconnects between layers in high density interconnect (HDI) designs, to accommodate the high input/output (I/O) density of advanced component packages and board designs. Sequential build-up (SBU) technology is used to fabricate HDI boards. The HDI layers are usually built up onto a traditionally manufactured double-sided core board or a multilayer PCB. As each HDI layer is built on to each side of the traditional PCB, µVias can be formed using: laser drilling, via formation, via metalization, and via filling. Because the hole is laser drilled, it has a cone shape.

If a connection required a path through multiple layers, the original approach was to stagger a series of µVias using a step-like pattern. Improvements in technology and processes now allow µVias to be stacked directly on top of each other.

Buried µVias are required to be filled, while blind µVias on the external layers do not require filling. Stacked µVias are usually filled with electroplated copper to make electrical interconnections between the multiple HDI layers and provide structural support for the outer level(s) of the µVia.

Definition of a µVia

Support for µVias

• The software supports two types of µVias:
  •  A µVia that traverses from one layer to an adjacent layer.
  • A Skip µVia, this type of µVia skips the adjacent layer, landing on the next copper layer after that.
• The Via Type is detected automatically based on the defined layer span, as shown in the image below.
• The order that the First layer and Last layer are chosen defines the drill direction for a µVia, as indicated by the direction of the conical µVia shape in the image.
• µVias are automatically stacked when traversing multiple layers during interactive routing (using available Via Types).

µVia Output Considerations

The PCB drill table and drill-type output files support µVias.

Drill Table

The PCB Drill Table includes µVia drill pairs.

The drill table identifies each hole by size, if the same size is used on multiple drill pair layers it is flagged as mixed.

Drill Fabrication Files

NC Drill - a separate file is created for each µVia drill pair.

Gerber X2 - specific setup entries for each µVia plot.

ODB++ - a separate drill fabrication file created for each µVia drill pair.

Back Drilling of Thru-hole Vias

Main article: Controlled Depth Drilling, or Back Drilling

Back drilling, which is also known as Controlled Depth Drilling (CDD), is a technique used to remove the unused portion, or stub, of copper barrel from a thru-hole in a printed circuit board. When a high-speed signal travels between PCB layers through a copper barrel, it can be distorted. If the signal layer usage results in a stub being present, and the stub is long, then that distortion can become significant.

These stubs can be removed by re-drilling those holes after the fabrication is complete, with a slightly larger drill. The holes are back drilled to a controlled depth, close to, but not touching, the last layer used by the via. Allowing for fabrication and material variations, a good fabricator can back drill holes to leave a 7 mil stub, and ideally, the remaining stub will be less than 10 mil.

   
By re-drilling the hole with an oversized drill bit to a specific depth the unused portion of the via barrel is removed, improving the integrity of this signal path.

Back Drilling is enabled in the Layer Stack Manager's Tools menu and then configured in the Back Drills tab of the Layer Stack Manager.