The Home | Design Rules button in the PCB editor opens the PCB Rules and Constraints Editor dialog, which includes controls you can use to manage the defined design rules for the current PCB document.
Design rules collectively form an instruction set for the PCB editor to follow. Each rule represents a requirement of your design and many of the rules, e.g., clearance and width constraints, can be monitored as you work with the Design Rule Checker dialog. Certain rules are monitored when using additional features of the software, such as routing-based rules when using the Situs Autorouter to route a design.
Design rules target specific objects and are applied in a hierarchical fashion. Multiple rules of the same type can be set up. It may arise that a design object is covered by more than one rule with the same scope. In this instance, a contention exists, which is resolved by a priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope(s) match the object(s) being checked.
With a well-defined set of design rules, you can successfully complete board designs with varying and often stringent design requirements. Since the PCB editor is rules-driven, taking the time to set up the rules at the onset of the design process will enable you to effectively get on with the job of designing with the knowledge that the rules system is working hard to ensure success.
Fundamentals of the PCB Rules System
The rules system built into the PCB editor has several fundamental features.
- Rules are separate from the objects - a rule is not added as an attribute of an object, but is rather added to the overall rule set and then scoped to apply to that object. This allows rules to be applied to multiple objects and modified or applied to different objects, which would otherwise be painful to do if having to change rule attributes at the individual object level.
- Rules are targeted (scoped) by writing a query - instead of using a set of fixed, predefined rule scopes, a flexible query system is used to define the objects to which a rule is applied. This gives precise control over the target of each and every design rule.
- Rules for any design situation - multiple rules of the same type can be defined and targeted to different sets of objects, allowing complete control over the definition of board constraints. For example, different width rules can be defined to route nets at different widths on different layers.
- Each rule has a priority - any design object can be targeted by multiple rules of the same type. To resolve any rule contention, the rule priority is used. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression(s) match the object(s) being checked.
- There are two types of rules - unary rules (rules that define the required behavior of an object) and binary rules (rules that define the interaction between two objects).
PCB Rules and Constraints Editor Dialog
This dialog allows you to browse and manage the design rules for the current PCB document.
In the folder-tree pane on the left, each of the supported design rule categories is listed under the Design Rules folder.
- Click on the root folder to access a summary listing of all specific rules that have been defined for all design rule types across all categories.
- Click on a category folder to access a summary listing of all specific rules that have been defined for all associated design rule types of that category.
- Click on a rule type folder to access a summary listing of all specific rules that have been defined for that type.
- Click on the entry for a specific rule or double-click on its entry in a summary list to access controls for managing its definition.
Right-click Menu
The following commands are available from the right-click menu of the left pane.
- New Rule - use to create a new rule of the currently selected rule type. The new rule will be added to the folder tree and will also appear in the summary list for that rule type. The rule name will appear bold to distinguish it as being new and yet to be 'applied'.
To access the scope and constraint attributes for the new rule, either click on the entry for the rule in the folder-tree pane or double-click on its entry in a summary list. The main editing window of the dialog will change to give access to the controls for defining the scope and constraint attributes for that rule.
When a new rule is added, it will initially be given a default name based on the specific type of rule. For example, if you add a new Clearance rule, the default name will be Clearance. If this default naming is not changed, adding another new rule of the same type will result in the same rule name with an incremented numerical suffix (i.e. Clearance_1, Clearance_2, etc.).
When a new rule is created for a particular rule type, it is automatically given priority 1 (the highest priority). If any other rules of that type exist, their priorities will be shifted (lowered) by one accordingly. They are then considered to be modified even though they may not have been specifically modified at the scope/constraint level. All such existing rules of that type will, therefore, be displayed in the modified state (bold with an asterisk).
- Duplicate Rule - use to quickly create an identical copy of the currently selected existing rule. The duplicate rule will be named the same as the original with the addition of a suffix (e.g., _1) to distinguish it. Its definition (scope, constraints, etc.,) will be identical to that of the original.
In terms of priority, the duplicate rule will be given the next priority below that of the original rule. For example, if the original rule has priority 1, the duplicate will be given priority 2.
- Delete Rule - use to delete the rule that is currently selected in the folder tree. The rule name will appear bold with strike-through highlighting to distinguish it as being a deletion that is yet to be 'applied'.
Many rule types have default rules created when a new PCB document is created. In a similar fashion, if all specific rules for one of those rule types are deleted, the default rule will be re-added automatically.
- Report - use to generate a report of currently defined design rules. The report can be for all rule categories, a specific rule category, or a specific rule type depending on the selected entry in the folder tree. The Report Preview dialog will open with the appropriate report already loaded. Use this dialog to inspect the report using various page/zoom controls before ultimately exporting it to file or printing it.
- Export Rules - use to export your favorite rule definitions to file. The Choose Design Rule Type dialog (described below) will open.
- Import Rules - use to import rule definitions from a previously save PCB rule file. The Choose Design Rule Type dialog (described below) will open.
When importing, if rules of a chosen type already exist, the option will be given to clear the existing rules prior to import. Clicking Yes results in all existing rules of that type being deleted and subsequently replaced with those in the .rul file. Clicking No will keep the existing rules. However, if existing rules and imported rules have the same name, the imported rules will overwrite the existing ones.
Main Editing Region
This region changes in accordance with what is currently selected in the left pane. It presents two different views.
- Summary Listing - if the Design Rules folder or any of the child rule categories or type folders are selected in the left-hand pane, this region presents a summary listing of all defined rules or all rules of the selected category or type. The summary listings also provide the following buttons.
- New Rule - click to create a new rule of the type currently selected in the folder-tree pane of the dialog.
- Delete Rule(s) - click to delete the specific rule or rules currently selected in the list. A deleted rule's name will appear bold with strike-through highlighting to distinguish it as being a deletion that is yet to be applied.
Multiple rules can be selected in a list using standard multi-select techniques (Ctrl+click, Shift+click).
- Duplicate Rule - click to quickly create an identical copy of the currently selected existing rule in the list.
- Report - click to generate a report containing all design rules in the currently displayed list. The Report Preview dialog will open with the report already loaded. Use this dialog to inspect the report using various page/zoom controls before ultimately exporting it to file or printing it.
A command to generate a report is also available from the right-click context menu for the region.
- Rule Definition - when a specific rule is selected in the left-hand pane, this region presents controls for defining the rule.
- Rule Scoping Controls - provides controls for determining the scope of the rule in terms of the objects to which it applies or between. See the Rule Scoping Controls section for details on using the controls in this region.
- Constraints - presents the constraints applicable to the type of rule being edited. Use the various controls to configure these constraints as required.
If a constraint for the rule is invalid, the rule's name will appear in red in both the folder-tree and summary listings. A warning message will also appear if you attempt to close this dialog.
Changes made to existing rule definitions are highlighted in both the folder-tree pane and the applicable summary lists. Such entries are distinguished by the rule name becoming bold and an asterisk displayed to the right of the name.
Rule Scoping Controls
When defining the scope of a design rule, you are essentially defining the member objects that are governed by the rule. Use the options available to set the scope as required. Depending on whether the rule is unary or binary, you will need to define one or two scopes.
For a unary design rule, controls will be provided to define a single rule scope. Use the options available in the Where The First Object Matches region. For a binary design rule, controls will also be provided to define a second rule scope. Use the options available in the Where The Second Object Matches region.
Controls are identical whether defining one or two rule scopes and are detailed in the following sections.
- Where The Object Matches - choose the desired scoping option.
- Top drop-down field - when using the Net (or Net and Layer) or Layer options, this field's drop-down will populate with all defined nets in the design or all currently enabled layers in the design. Choose the required target accordingly.
- Bottom drop-down field - when using the Net and Layer option, this field's drop-down will populate with all currently enabled layers in the design. Choose the required layer accordingly.
- Priorities - click to open the Edit Rule Priorities dialog (described below) in which you can manage the priorities of multiple rules of the same rule type.
Multiple rules of the same type can be set up. It may arise that a design object is covered by more than one rule with the same scope. In this instance, a contention exists, which is resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope(s) match the object(s) being checked.
Choose Design Rule Type Dialog
This dialog is used to specify one or more rule types to be imported into or exported from a .Rul file from the currently defined set of design rules for the board.
Select the required rule type (or multiple types when exporting/importing) then click OK.
When exporting selected rule types, clicking OK will open the Export Rules to File dialog in which you can define where, and under what name, the resulting rule file (*.Rul) is to be saved. When importing selected rule types, clicking OK will access the Import File dialog from which you can browse to and open the required rule file (*.Rul).
Edit Rule Priorities Dialog
This dialog provides controls to manage the priority of rules within a chosen rule category. It is the rule priority that defines the order in which multiple rules of the same type are applied when, for example, performing a Design Rule Check. Rule priority simplifies the process of defining and managing rules, the idea being to define general rules that cover broad requirements and then override these with specific rules in specific situations. The dialog is accessed from the PCB Editor by clicking the Priorities button at the bottom of the PCB Rules and Constraints Editor dialog.
It may arise that a design object is covered by more than one rule with the same scope. In this instance, a contention exists. All contentions are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression(s) match the object(s) being checked.
Options/Controls
- Rule Type - use the drop-down to choose the specific rule type for whose defined rules you want to manage the priorities. Note that all rule types are listed regardless of whether or not rules of a particular type actually exist.
Initially, the dialog will list all rule instances for the rule type that is currently selected in the PCB Rules and Constraints Editor dialog.
- Priority Listing - this region presents a list of all currently defined rules of the chosen type. Rules are listed in order of priority with the highest priority (1) at the top of the list. For each rule, read-only information is listed.
- Increase/Decrease Priority - click to increase/decrease the priority of the selected design rule (where applicable).
Applicable Unary/Binary Rules Dialogs
These dialogs include controls to quickly access information about which unary/binary design rules apply to the chosen object(s) in the design space. Unary rules apply to one object. Binary rules apply to two objects, or between an object in one set to any object in a second set. Therefore, binary design rules have two rule scopes.
Right-click over any placed design object in the design space then click Applicable Unary Rules or Applicable Binary Rules from the context menu. If Applicable Binary Rules is chosen, you will be prompted to select two objects in the design. Position the cursor over each object in turn then click or press Enter.
If the two chosen objects do not have any binary rules applied to them, the dialog will not open.
Options/Controls
- Unary/Binary Rules List - this region confirms the chosen design object(s) being 'interrogated' and lists all defined design rules, by rule type, that could be applied to the object(s)s. The specific constraints for each rule are also displayed. Each rule will have either a green check or a red X next to it. A check indicates that this is the rule with the highest priority out of all applicable rules of the same type and is the rule currently applied. Lower priority rules of the same type are listed with an X next to them, indicating that they are applicable but, since they are not the highest priority rule, they are not currently applied. Any rules that would apply to the objects but are currently disabled also have an X next to them and are shown using strike-through highlighting.
- Design Rules - this button becomes available when a rule entry is selected in the main list. Click it to open the PCB Rules and Constraints Editor dialog (described above).
If rather than seeing which rules apply between two objects you would prefer to pick a rule and see to which objects that rule applies, use the
PCB Rules And Violations panel. As you click on a specific rule in the
Rules region of the panel, filtering will be applied using the rule as the scope of the filter. Only those design objects that fall under the scope of the rule will be filtered, the visual result of which (in the main design space) is determined by the highlighting options enabled (
Mask/Dim/Normal,
Select,
Zoom).
Design Rules Categories
Electrical Rules
Clearance
Rule classification: Binary
This rule defines the minimum clearance allowed between any two primitive objects on a copper layer. Either a single value for clearance can be specified, or different clearances for different object pairings through use of a dedicated Minimum Clearance Matrix. The latter, in combination with rule-scoping, provides the flexibility to build a concise and targeted set of clearance rules to meet even the most stringent of clearance needs.
Constraints
- Connective Checking – the scope of the rule with respect to the nets in the design. Can be set to one of the following:
Different Nets Only – constraint is applied between any two primitive objects belonging to different nets (e.g., two tracks on two different nets).Same Net Only – constraint is applied between any two primitive objects belonging to the same net (e.g., between a via and pad on the same net).Any Net – constraint is applied between any two primitive objects belonging to any net in the design. This is the most comprehensive of the options and covers the possibility of the objects belonging to the same net or different nets.- Different Differential Pair - constraint is applied between any two primitive objects belonging to different nets of different differential pairs (e.g., a track in TX_P and a track in RX_P).
- Same Differential Pair - constraint is applied between any two primitive objects belonging to different nets of the same differential pair (e.g., a track in TX_P and a track in TX_N).
- Minimum Clearance – the value for the minimum clearance required. A value entered here will be replicated across all cells in the Minimum Clearance Matrix. Conversely, when a different clearance value is entered for one or more object pairings in the matrix, the Minimum Clearance constraint will change to N/A to reflect that a single clearance value is not being applied across the board.
- Minimum Clearance Matrix – provides the ability to fine-tune clearances between the various object-to-object clearance combinations in the design.
The default Clearance rule for a new PCB document will default to use 10mil for all object-to-object clearance combinations. When creating a subsequent new clearance rule, the matrix will be populated with the values currently defined for the lowest priority Clearance rule.
Working with the Clearance Matrix
Definition of clearance values in the matrix can be performed in the following ways:
- Single-cell editing - to change the minimum clearance for a specific object pairing. Click on a cell to select it for editing.
- Multi-cell editing - to change the minimum clearance for multiple object pairings:
- Use Ctrl+click, Shift+click, and click&drag to select multiple cells in a column.
- Use Shift+click, and click&drag to select multiple contiguous cells in a row.
- Use click&drag to select multiple contiguous cells across multiple rows and columns
- Click on a row header to quickly select all cells in that row.
- Click on a column header to quickly select all cells in that column.
To set a single clearance value for all possible object pairings, set the required value for the Minimum Clearance constraint. Upon clicking Enter, this value will be replicated across all applicable cells of the matrix. Alternatively, click the blank gray cell at the top-left of the matrix or use the Ctrl+A shortcut. This selects all cells in the matrix, ready to accommodate a newly-entered value.
With the required selection made (either a single cell or multiple cells), making a change to the current value is simply a case of typing the new value required. To submit the newly entered value, either click away on another cell or press Enter. All cells in the selection will be updated with the new value.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scopes match the objects being checked.
Rule Application
Online DRC, Batch DRC, interactive routing, autorouting, and during polygon placement.
Notes
- When defining the constraints for the rule, the Connective Checking option would typically be set to
Different Nets Only. An example of when Same Net Only or Any Net could be used is to test for vias being placed too close to pads or other vias on the same net or any other net.
- The minimum clearance matrix applies regardless of the connective checking method specified (Different Nets Only, Same Net Only, Any Net). If different clearances are required between objects on the same net to those defined for objects on different nets, be sure to define separate clearance rules as required to suit.
Short-Circuit
Rule classification: Binary
This rule tests for short circuits between primitive objects on the copper (signal and plane) layers. A short circuit exists when two objects touch that have different net names.
Constraints
Allow Short Circuit defines whether the target nets falling under the two scopes (full queries) of the rule can be short-circuited or not. If you require two different nets to be shorted together, for example, when connecting two ground systems within a design, ensure that this option is enabled.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scopes match the object(s) being checked.
Rule Application
Online DRC, Batch DRC, and during autorouting.
Un-routed Net
Rule classification: Unary
This rule tests the completion status of each net that falls under the scope (full query) of the rule. If a net is incomplete, each completed section (sub-net) is listed along with the routing completion. The routing completion is defined as:
(connections complete / total number of connections) x 100
Constraints
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
Batch DRC.
Notes
Some split plane DRC checks require the Un-Routed Net rule to be Batch-enabled for them to work.
Un-Connected Pin
Rule classification: Unary
This rule detects pins that have no net assigned and no connecting tracks.
Constraints
None.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
Online DRC and Batch DRC.
Modified Polygon
Rule classification: Unary
This rule detects polygons that are still shelved and/or have been modified but have not yet been poured.
Constraints
When Allow unpoured is enabled, all polygons that are currently modified but have not been poured will not be flagged as a violation.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Routing Rules
Width
Rule classification: Unary
This rule defines the width of tracks placed on the copper (signal) layers.
Constraints
- Min Width – specifies the minimum permissible width to be used for tracks when routing the board.
- Preferred Width – specifies the preferred width to be used for tracks when routing the board.
- Max Width – specifies the maximum permissible width to be used for tracks when routing the board.
The values specified for Min Width, Preferred Width, and Max Width will apply to all signal layers.
- Check Tracks/Arcs Min/Max Width Individually – checks individual widths of tracks and arcs fall within the minimum and maximum range.
- Check Min/Max Width for Physically Connected – checks that the width of routed copper formed by a combination of tracks, arcs, fills, pads, and vias falls within the minimum and maximum range.
- Layer Attributes Table – displays all signal layers. The minimum, maximum and preferred routing widths are displayed, as well as other layer-specific information. The routing width fields can be set globally by defining a value in the individual width constraint fields, or individually by typing a width value directly into the table.
When defining values for the minimum, maximum and preferred routing widths, the Layer Attributes Table will highlight any invalid entries with red text. This could happen, for example, when you specify a minimum constraint value that is greater than the maximum constraint value. The incorrect rule definition is further highlighted by the rule name becoming red in both the folder-tree pane and the respective summary lists.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
The Preferred Width setting is obeyed by the Autorouter.
The Min Width and Max Width settings are obeyed by the Online DRC and Batch DRC. They also determine the range of permissible values that can be used during interactive routing (press Tab key while routing to change the trace width within the defined range). If a value is entered outside of this range, a dialog will appear alerting you to this fact. You will be prompted to either continue, in which case the value will automatically be clipped, or cancel and change the value manually.
Note
Default, hardcoded impedance equations are in place to calculate - for both Microstrip and Stripline - the impedance and the required trace width in order to satisfy that impedance when routing.
Microstrip
- Calculated Impedance - the default formula is:
(60/SQRT(Er*(1-EXP(-1.55*(0.00002+TraceToPlaneDistance)/TraceToPlaneDistance))))*LN(5.98*TraceToPlaneDistance/(0.8*TraceWidth+TraceHeight))
- Calculated Trace Width - the default formula is:
((5.98*TraceToPlaneDistance)/EXP(CharacteristicImpedance/(60/SQRT(Er*(1-EXP(-1.55*(0.00002+TraceToPlaneDistance)/TraceToPlaneDistance)))))-TraceHeight)/0.8
Note that if the plane layer is not adjacent to the signal layer, the nearest plane layer will be used in the calculations.
Stripline
- Calculated Trace Width - the default formula is:
((1.9*(2*TraceToPlaneDistance+TraceHeight))/(EXP((CharacteristicImpedance/(80/SQRT(Er)))/(1-(TraceToPlaneDistance/(4*(PlaneToPlaneDistance-TraceHeight-TraceToPlaneDistance))))))-TraceHeight)/0.8
Note that if the plane layers are not adjacent to the signal layer, the nearest plane layers will be used in the calculations. Note also that an offset stripline configuration is not supported.
Routing Topology
Rule classification: Unary
This rule specifies the topology to be employed when routing nets on the board. The topology of a net is the arrangement or pattern of the pin-to-pin connections. By default, pin-to-pin connections of each net are arranged to give the shortest overall connection length. A topology is applied to a net for a variety of reasons: for high-speed designs where signal reflections must be minimized the net is arranged with a daisy chain topology, or for ground nets, a star topology could be applied to ensure that all tracks come back to a common point.
Constraints
- Topology – defines the topology to be used for the net(s) targeted by the scope (full query) of the rule. The following topologies can be applied:
Shortest – this topology connects all nodes in the net to give the shortest overall connection length.Horizontal – this topology connects all the nodes together, preferring horizontal shortness to vertical shortness by a factor of 5:1. Use this method to force routing in the horizontal direction.Vertical – this topology connects all the nodes together, preferring vertical shortness to horizontal shortness by a factor of 5:1. Use this method to force routing in the vertical direction.Daisy-Simple – this topology chains all the nodes together, one after the other. The order they are chained is calculated to give the shortest overall length. If a source and terminator pad are specified, all other pads are chained between them to give the shortest possible length. Edit a pad to set it to be a source or terminator. If multiple sources (or terminators) are specified, they are chained together at each end.Daisy-MidDriven – this topology places the source node(s) in the center of the daisy chain, divides the loads equally, and chains them off either side of the source(s). Two terminators are required, one for each end. Multiple source nodes are chained together in the center. If there are not exactly two terminators, the Daisy-Simple topology is used.Daisy-Balanced – this topology divides all the loads into equal chains; the total number of chains equal to the number of terminators. These chains then connect to the source in a star pattern. Multiple source nodes are chained together.Starburst – this topology connects each node directly to the source node. If terminators are present, they are connected after each load node. Multiple source nodes are chained together, as in the Daisy-Balanced topology.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
During autorouting.
When using the Autorouter, routing completion time may be longer when using topologies other than Shortest.
Routing Priority
Rule classification: Unary
This rule assigns a routing priority to the net(s) targeted by the rule. The Autorouter uses the assigned priority value to gauge the routing importance of each net in the design and, therefore, determine which nets should be routed first.
Constraints
The Routing Priority is the priority value assigned to the net(s) targeted by the scope (full query) of the rule. Enter a value between 0 and 100, where the higher the number assigned, the greater the priority when routing.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
During autorouting.
Routing Layers
Rule classification: Unary
This rule specifies which layers are allowed to be used for routing.
Constraints
Enabled Layers lists each of the signal layers currently defined for the design as defined by the layer stackup. Use the associated Allow Routing option to enable/disable routing on a layer, as required.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
During interactive routing and autorouting.
The rule is also obeyed by the Online DRC and Batch DRC.
Note
When using the Autorouter, the routing direction for each enabled signal layer in the design is defined as part of the Situs Autorouter setup. Directions are specified in the Layer Directions dialog, which is accessed by clicking the Edit Layer Directions button in the Situs Routing Strategies dialog.
Setting the routing direction for a layer to Any can affect performance when autorouting. More efficient use of board area may be achieved by choosing a specific routing direction.
Routing Corners
Rule classification: Unary
This rule specifies the corner style to be used during autorouting.
Constraints
- Style – specifies which routing corner style to use.
- Setback – these two fields allow you to define a minimum and maximum value for the setback when using the
45 Degrees and Rounded corner styles. The setback is the distance from the 'true' corner location (that which would exist if using the 90 Degrees style) to the point at which the Autorouter should begin chamfering or rounding; in effect, controlling miter size or corner radius.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
This rule is intended for use by third-party Autorouters that implement 45° routing as a post-process. It is not followed by the Situs Autorouter, which implements 45° routing as a native process.
Routing Via Style
Rule classification: Unary
This rule specifies the routing via diameter and hole size.
Constraints
- Via Diameter– specifies constraint range values to be adhered to with respect to the diameters of vias placed when routing the board.
- Via Hole Size– specifies constraint range values to be adhered to with respect to the hole sizes of vias placed when routing the board.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
The Preferred via attributes are used by the Autorouter.
The Minimum and Maximum via attributes are obeyed by the Online DRC and Batch DRC. They also determine the range of permissible values that can be used during interactive routing, when you press the * shortcut key to toggle routing signal layers, or when you press the / shortcut key to connect to a plane layer. Press the Tab key while routing to change a value within its defined range. If a value is entered outside of its range, a dialog will appear alerting you to this fact. You will be prompted to either continue, in which case the value will automatically be clipped, or cancel and change the value yourself.
Fanout Control
Rule classification: Unary
This rule specifies fanout options to be used when fanning out the pads of surface mount components in the design that connect to signal and/or power plane nets. Fanout essentially turns an SMT pad into a thru-hole pad, from a routing point of view, by adding a via and connecting track. This greatly increases the probability of successfully routing the board since a signal is made available to all routing layers instead of just the top or bottom layer. This is particularly needed in high-density designs where routing space is very tight.
Constraints
- Fanout Style – specifies how the fanout vias are placed in relation to the SMT component. The following options are available:
Auto – chooses the style most appropriate for the component technology and in order to give optimal routing space results.Inline Rows – fanout vias are placed within two aligned rows.Staggered Rows – fanout vias are placed within two staggered rows.BGA – fanout occurs in accordance with the specified BGA Options.Under Pads – fanout vias are placed directly under SMT component pads.
- Fanout Direction – specifies the direction to use for the fanout. The following options are available:
Disable – do not allow fanout with respect to the SMT components targeted by the rule.In Only – fanout in an inward direction only. All fanout vias and connecting tracks will be placed within the component's bounding rectangle.Out Only – fanout in an outward direction only. All fanout vias and connecting tracks will be placed outside of the component's bounding rectangle.In Then Out – fanout all component pads in an inward direction to begin with. All pads that cannot be fanned out in this direction should be fanned out in an outward direction (if possible).Out Then In – fanout all component pads in an outward direction to begin with. All pads that cannot be fanned out in this direction should be fanned out in an inward direction (if possible).Alternating In and Out – fanout all component pads (where possible) in an alternating fashion, first inward then outward.
- Direction From Pad – specifies the direction to use for the fanout. When a BGA component is fanned out, its pads are sectioned into quadrants, with fanout applied to the pads in each quadrant simultaneously. The following options are available:
Away From Center – fanout for pads in each quadrant is applied following a 45° angle away from the component's center.North-East – all pads, in each quadrant, are fanned out in a North-Easterly direction (45° counterclockwise from the horizontal).South-East – all pads, in each quadrant, are fanned out in a South-Easterly direction (45° clockwise from the horizontal).South-West – all pads, in each quadrant, are fanned out in a South-Westerly direction (135° clockwise from the horizontal).North-West – all pads, in each quadrant, are fanned out in a North-Westerly direction (135° counterclockwise from the horizontal).Towards Center – fanout for pads in each quadrant is applied following a 45° angle toward the component's center. In most cases, uniformity of direction will not be possible due to the required fanout space already taken by another pads' fanout via. In these cases, fanout will occur in the next available direction (North-East, South-East, South-West, North-West).
- Via Placement Mode – specifies how the fanout vias are placed in relation to the pads of the BGA component. The following options are available:
Close To Pad (Follow Rules) – fanout vias will be placed as close to their corresponding SMT component pads as possible without violating defined clearance rules.Centered Between Pads – fanout vias will be centered between the SMT component pads.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
During interactive routing and autorouting.
Notes
- The following default Fanout Control design rules are automatically created, covering the typical component package types available (listed in descending order of priority). These rules can be edited or others defined in accordance with your individual design requirements.
- Fanout_BGA
- Fanout_LCC
- Fanout_SOIC
- Fanout_Small
- Fanout_Default – with a scope of
All.
- The style used for the fanout vias will follow the applicable Routing Via Style design rule(s). Additional track laid down as part of the fanout process from pad to via will follow the applicable Routing Width design rule(s).
Differential Pairs Routing
Rule classification: Unary
This rule defines the routing width of each net in a differential pair and the clearance (or gap) between the nets in that pair. Differential pairs are typically routed with specific width-gap settings to deliver the required single-ended and differential impedance needed for that net-pair.
Constraints
- Min Width - specifies the minimum permissible width to be used for tracks when routing the differential pair.
- Min Gap - specifies the minimum permissible clearance between primitives on different nets within the same differential pair.
- Preferred Width - specifies the preferred width to be used for tracks when routing the differential pair.
- Preferred Gap - specifies the preferred clearance between primitives on different nets within the same differential pair.
- Max Width - specifies the maximum permissible width to be used for tracks when routing the differential pair.
- Max Gap - specifies the maximum permissible clearance between primitives on different nets within the same differential pair.
- Max Uncoupled Length - specifies the value for the maximum permissible uncoupled length between positive and negative nets within the differential pair.
- Layer Attributes Table - displays all signal layers or only those defined in the layer stack. The minimum, maximum and preferred width and gap constraints are displayed as well as other layer-specific information. The width and gap fields can be set globally for all layers by defining values using the controls to the right of the graphic or individually by typing width and gap values directly into the table.
When defining values for the minimum, maximum and preferred width and/or gap, the Layer Attributes Table will highlight any invalid entries by using red text. This could happen, for example, when you specify a minimum constraint value that is greater than the maximum constraint value, or when setting a preferred constraint value that is lower than the minimum or above the maximum constraint values. The incorrect rule definition is further highlighted by the rule name becoming red in both the folder-tree pane and the respective summary lists.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.
Rule Application
Online DRC, Batch DRC, interactive routing (and re-routing), autorouting, interactive length tuning (Min Gap is applied), and when interactively modifying the pair, such as sliding a track segment of one of the nets in the pair.
Notes
- While the width of each net in a differential pair is monitored by the applicable Differential Pairs Routing rule (and not by a Width rule), clearance checking between the nets in that pair is still governed by the applicable Clearance design rule. In other words, a Clearance rule must be defined that targets the differential pair (on the specific layer where needed) with its connective checking mode set to Same Differential Pair, and whose clearance is set to be equal to or lower than the value for the Min Gap constraint defined for that layer as part of the applicable Differential Pairs Routing rule.
- The clearance from a net in a differential pair to any other electrical object that is not a part of the pair is monitored by the applicable Clearance rule.
- While the optimal width-gap settings may be achievable for most of the board, there will often be areas, such as under a BGA component, where smaller and tighter width-gap settings must be used. As well as switching the Width-Gap settings interactively, this requirement can also be achieved by defining multiple differential pair routing rules - a lower-priority rule that targets the differential pair across the board, and a higher-priority rule that targets the differential pair in specific areas. You then target the differential pair in a specific area by defining a Room Definition rule and use that room as part of the scope of a differential pair routing rule.
Mask Rules
Solder Mask Expansion
Rule classification: Unary
The shape that is created on the solder mask layer at each pad and via site is the pad or via shape expanded or contracted radially by the amount specified by this rule.
Constraints
Expansion is the value applied to the initial pad/via shape to obtain the final shape on the solder mask layer. Enter a positive value to expand the initial pad/via shape; enter a negative value to contract it.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
During output generation.
Note
Partial and complete tenting of pads and vias can be achieved by defining the appropriate value for the Expansion constraint.
- To partially tent a pad/via, covering the land area only, set Expansion to a negative value that will close the mask right up to the pad/via hole.
- To completely tent a pad/via, covering the land and hole, set Expansion to a negative value equal to or greater than the pad/via radius.
- To tent all pads/vias on a single layer, set the appropriate Expansion value and ensure that the scope of the rule targets all pads/vias on the required layer.
- To completely tent all pads/vias in a design in which varying pad/via sizes are defined, set Expansion to a negative value equal to or greater than the largest pad/via radius.
Solder mask expansion can be defined for pads and vias on an individual basis in the associated mode of the Inspector panel.
Paste Mask Expansion
Rule classification: Unary
The shape that is created on the paste mask layer at each pad site is the pad shape expanded or contracted radially by the amount specified by this rule.
Constraints
Expansion is the value applied to the initial pad shape to obtain the final shape on the paste mask layer. Enter a positive value to expand the initial pad shape; enter a negative value to contract it.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
During output generation.
The paste mask expansion can be defined for pads on an individual basis in the associated mode of the Inspector panel.
Plane Rules
Power Plane Connect Style
Rule classification: Unary
This rule specifies the style of the connection from a component pin to a power plane.
Constraints
- Connect Style – defines the style of the connection from a pin of a component, targeted by the scope of the rule, to a power plane. The following three styles are available:
Relief Connect – connect using a thermal relief connection.Direct Connect – connect using solid copper to the pin.No Connect – do not connect a component pin to the power plane.
The following constraints apply only when using the Relief Connect style:
- Conductors – the number of thermal relief copper connections (2 or 4).
- Expansion – the radial width measured from the edge of the hole to the edge of the air gap.
- Air-Gap – the width of each air gap in the relief connection.
- Conductor Width – how wide the thermal relief copper connections are.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
During output generation.
Note
Power planes are constructed in the negative in the PCB Editor, so a primitive placed on a power plane layer creates a void in the copper.
Power Plane Clearance
Rule classification: Unary
This rule specifies the radial clearance created around vias and pads that pass through but are not connected to a power plane.
Constraints
Clearance is the value for the radial clearance.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
During output generation.
Polygon Connect Style
Rule classification: Binary
This rule specifies the style of the connection from a component pin to a polygon plane.
Constraints
Connect Style – defines the style of the connection from a pin of a component, targeted by the scope of the rule, to a polygon plane.
The following constraints apply only when using the Relief Connect style:
- Conductors – the number of thermal relief copper connections (2 or 4).
- Angle – the angle of the copper connections (45° or 90°).
- Air Gap Width – the distance between the edge of the pad and the surrounding polygon.
- Conductor Width – how wide the thermal relief copper connections are.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
During polygon pour.
Placement Rules
Component Clearance
Rule classification: Binary
This rule specifies the minimum distance that components can be placed from each other. Component clearance includes clearance between 3D models used to define component bodies (extruded (simple) types). In the absence of 3D bodies, the primitives on the silk and copper layers (excluding Designator and Comment) are used to define the object shape and size along with the height value specified in the component properties.
Component clearance is calculated using accurate 3D meshing to define shape and contour for the component through its associated 3D body objects. These may be extruded 2D shapes. It is evident that using 3D bodies provides the greatest accuracy when it comes to clearance checking, particularly in the vertical sense and in the context of complex component shapes.
The Component Clearance rule does not check for clearance violations between 3D bodies and the board surface.
Constraints
- Vertical Clearance Mode – two modes for specifying vertical clearance are available:
- Infinite – clearance checking is performed using a value representing infinity. This means that any components placed above or below will be in violation. An example of use would be a board that has an adjustment mechanism that must remain accessible. Using this rule on that component will cause a violation against any components that protrude into the area above or below the component.
- Specified – clearance checking is performed using the exact shape defined by the component 3D bodies or component footprint properties. When using 3D bodies from which to make the check, it is possible to have an acceptable overhang between one component over another, provided they are not in violation. With this mode enabled, the following constraint becomes available:
- Minimum Vertical Clearance – the value for the minimum permissible clearance, in the vertical sense, between placed components in the design.
- Minimum Horizontal Clearance – the value for the minimum permissible clearance, in the horizontal plane, between placed components in the design.
- Show actual violation distances – enable to show lines between the points of greatest violation between components. The distance of the line is displayed and can be useful in calculating the distance required to move an object to resolve the violation.
Enabling the Show actual violation distances option may reduce performance on some systems.
- Do not check components without 3D body - enable to not check components without a 3D body.
- Check clearance by component boundary - enable to check the clearance by the component boundary.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scopes match the object(s) being checked.
Rule Application
Online DRC and Batch DRC.
Notes
- An extruded (simple) 3D body is a polygonal-shaped object that can be placed in a library component or a PCB document on any enabled mechanical layer. In a component footprint, it can be used to specifically define the physical size and shape of a component in the X, Y and Z axes.
- Multiple 3D body primitives may be used to define shapes of any complexity. This can prove especially useful in the vertical sense because it allows you to vary the height of a component in different regions of that component.
Component Orientations
Rule classification: Unary
This rule specifies allowable component orientations. Multiple orientations are permitted, allowing component placement in accordance with any of the enabled orientations. This could be used, for example, when a component is only allowed a particular orientation for wave soldering; perhaps its pads are prone to forming solder bridges during soldering if it is oriented into the wave, so a rule of this type could be added to only mount it so it enters with the pads across the wave. Another example could be RF objects (antennas) that have to be particularly aligned.
Constraints
- Allowed Orientations - the chosen orientations that are made available for use. The following orientation-based options are available:
- 0 Degrees - permits rotation of placed components to the 0° orientation.
- 90 Degrees - permits rotation of placed components to the 90° orientation.
- 180 Degrees - permits rotation of placed components to the 180° orientation.
- 270 Degrees - permits rotation of placed components to the 270° orientation.
- All Orientations - permits rotation of placed components to any of the four individual orientations.
In each case, rotation is relevant to the orientation of the component in the source library.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.
Rule Application
Currently not observed by the DRC system.
Permitted Layers
Rule classification: Unary
This rule specifies the layers on which components can be placed.
Constraints
- Permitted Layers - the layers permitted to be used when placing components. The following layer options are available:
- Top Layer - allow component placement on the top layer.
- Bottom Layer - allow component placement on the bottom layer.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.
Rule Application
Batch DRC.
Note
The rule acts as a test when performing a Batch DRC to ensure components that are targeted by the query expression of the rule's scope are being placed only on a permitted layer. Parameters specified for components on the schematic, and that have been brought across into footprints on the PCB, can be used to great effect for this very purpose. For example, to check that components that do not support wave soldering are not placed on the bottom layer, a rule of this type can be defined. If we consider a component parameter, SupportsWaveSolder, has been defined for components and brought across as parameters of the footprints in the PCB, then the rule scope might be:
CompParameterValue('SupportsWaveSolder') <> 'Yes'
and only the Top Layer constraint would be permitted, with the Bottom Layer constraint disabled.
Height
Rule classification: Unary
This rule defines height restrictions for components placed within the design.
Constraints
- Minimum – the value for the minimum permissible component height.
- Preferred – the value for the preferred component height.
- Maximum – the value for the maximum permissible component height.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope matches the object(s) being checked.
Rule Application
The Preferred setting is obeyed when displaying the board in 3D. The Minimum and Maximum settings are obeyed by the Online DRC and Batch DRC.
Notes
- The height property for a component is defined in the associated mode of the Inspector panel.
- Alternatively, the height is taken from the highest 3D body object included in the component footprint.
