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Retired Documentation No Longer Applicable to a Later Version of Altium Designer
Retired Documentation - Design Rules
Working with the Slope - Falling Edge Design Rule on a PCB in Altium Designer
Created: 二月 22, 2016 | Updated: 四月 11, 2017
| Applies to versions: 16.0, 16.1, 17.0 and 17.1
您正在阅读的是 17.1. 版本。关于最新版本，请前往 Working with the Slope - Falling Edge Design Rule on a PCB in Altium Designer 阅读 21 版本
Rule category: Signal Integrity
Rule classification: Unary
Summary
This rule specifies the maximum allowable slope time on the falling edge of the signal. Falling edge slope is the time it takes for a signal to fall from the threshold voltage (VT), to a valid low (VIL). Constraints.
Constraints
Default constraints for the Slope - Falling Edge rule.
- Maximum (seconds) - the value for the maximum permissible falling edge slope time.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.
Rule Application
Batch DRC and during Signal Integrity analysis.