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Retired Documentation No Longer Applicable to a Later Version of Altium Designer
Retired Documentation - Design Rules
Working with the Hole To Hole Clearance Design Rule on a PCB in Altium Designer
Created: 二月 22, 2016 | Updated: 十月 23, 2018
| Applies to versions: 16.0, 16.1, 17.0 and 17.1
您正在阅读的是 16.1. 版本。关于最新版本，请前往 Working with the Hole To Hole Clearance Design Rule on a PCB in Altium Designer 阅读 21 版本
Rule category: Manufacturing
Rule classification: Binary
Summary
This rule ensures checking of manufacturing compatibility of drilled holes. When enabled, it will flag any multiple vias / pads at the same location, or overlapping pad / via holes. There is also an option to determine whether stacked micro vias are allowed or not.
Constraints
Default constraints for the Hole To Hole Clearance rule.
- Allow Stacked Micro Vias - enable this option to allow micro vias to be stacked.
- Hole To Hole Clearance - the value for the minimum permissible clearance between pad/via holes in the design.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expressions match the object(s) being checked.
Rule Application
Online DRC and Batch DRC.