xSignal的设计规则支持
Design rules are how you translate your requirements into a set of instructions that the PCB editor can understand and obey. Rules can be checked during object placement, referred to as Online DRC, or as a post-process, referred to as Batch DRC. xSignals can be used to define the objects to which a design rule must be applied.
► Learn more about Design Rules
► Learn more about Length Tuning
Matched Length Rule
The Matched Length design rule is used to ensure that the length of the specified nets is within the specified range. This rule is essential in a high-speed design, where the challenge is not just about how long it takes the signals to arrive (which is determined by their overall length), but how important it is that the specified signals arrive at the same. Depending on the signal switching speeds, the function of the signal, and the materials used in the board, the allowed difference could be as much as 500mils, or as little as 1mil.
The image below shows an example of the Matched Length design rule configured to target the xSignals in the xSignal class PCIE, and test for a difference in lengths within each differential pair in that xSignals class. Each pair in the class must have routed lengths that result in a Delay Tolerance of no more than 2ps delay between the two nets in that pair.
Note that the Matched Length design rule Constraints requires you to select between matching the length of all targeted nets (Group Matched Lengths), or matching the two nets within each diff pair in the targeted nets.
The image below shows the PCIE_TX xSignal class selected in the panel, and those xSignals selected in the design space.
As well as the PCIE class, there are also classes defined for the TX and RX pairs. Note that one of the TX xSignals fails the applicable matched length rule. ##
If you plan to length tune xSignals which include single nets and differential pairs, create the following rules:
- A matched length rule that defines the length matching requirements between nets and differential pairs in xSignals. To configure the rule to test the length of one net/pair against the length of another net/pair, enable the Group Matched Lengths option.
- A second, higher-priority matched length rule that defines the within-pair length matching requirements. To configure the rule to test the length of one pair-member against the other pair-member, enable the Within Differential Pair Length option.
A good approach to tune the lengths of such xSignals is to:
- Route the nets and differential pairs of the xSignal.
- Length tune the single nets using the Interactive Length Tuning command.
- Length tune between the pairs using the Interactive Differential Pair Length Tuning command. Length tuning uses the longest signal length in the longest pair as the Target Length, and tunes the longest net in the pair to this length.
- Length tune the shorter net within each pair against the other net in the pair using the Interactive Length Tuning command.
- Now you can use the PCB Rules and Violations panel to check the within-pair Matched Net Length rule(s). To do this, select Matched Net Lengths in the Rule Classes section of the panel, then right-click on the required Matched Length rule and select the Run DRC Rule <RuleName> command from the context menu. Adjust the single-net tuning accordions if required.
- Then use the PCB Rules and Violations panel to check the between-pair Matched Net Length rule(s), using the process just described. Adjust the differential pair tuning accordions if required.
Length Rule
The Length design rule is used to ensure that the overall routed length is within the specified range. This rule is typically used to ensure that the target nets are no longer than the specified length, for example, to ensure that the circuit timing requirements will be met. The length rule respects the xSignal type queries listed above.
Return Path Rule
The Return Path design rule checks for a continuous signal return path on the designated reference layer above or below the signals targeted by the rule. The return path can be created from fills, regions and polygon pours placed on a signal layer, or it can be a plane layer.
The return path layers are the reference layers defined in the selected Impedance Profile. Add a new Return Path design rule in the High Speed rule category.
The image below shows a Return Path rule violation, where the xSignal return path polygon has a hole for a via to pass through.
Using the PCB Rules and Violations panel to locate a Return Path rule violation. ##
Accurate Length Calculations
A key requirement of defining high-speed design rules is an accurate calculation of the route lengths. The traditional approach to calculating signal length is to add up the centerline length of all segments used in a route, as well as the vertical distance due to the height of the vias, which was originally determined by the board thickness.
This approach is not adequate for a high-speed design for a number of reasons, including:
- Stacked and overlapping objects - an algorithm that simply adds the centerline length of all objects in a net does not cater for stacked or overlapped objects.
- Wandering route path within an object - there are often routing objects completely within a pad or via, which can falsely add to the length, as shown in the first image below. The second image shows the correct way to calculate the length when a fill object is part of the routing.
- Via length - blind and buried vias do not traverse all layers of the board, so the board thickness is not sufficiently accurate to determine the vertical length. The actual via height must be used, taking into consideration the copper and insulation thicknesses that the via passes through.
The PCB editor's length calculator returns the most accurate route length possible.
The length calculation is accurately calculated along the centerline of the shortest path, as shown in these two images.
Accurate lengths, based on the layers traversed and the stackup dimensions, are calculated for vias. Image from the PCB panel in Nets mode.